3D NoC using through silicon Via: An asynchronous implementation
3D NoC using through silicon Via: An asynchronous implementation
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使用硅通孔的 3D NoC：异步实现
DOI：
10.1109/vlsisoc.2011.6081643
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
F. Clermidy
中科院分区：
文献类型：
--
作者：
P. Vivet;D. Dutoit;Y. Thonnart;F. Clermidy
3D堆叠被视为最有趣的芯片（SOC）开发技术之一。但是，使用硅VIA（TSV）使用的3D技术尚未证明其在大型产品中部署的生存能力。在本文中，我们正在研究3D芯片上的3D网络具有有希望的解决方案，以提高模块化和可伸缩性。我们表明，基于异步逻辑的有效实现仅为700 TSV提供64GB/s的可用带宽，在简化汇编过程的同时，优于经典接口。我们还指出，与经典的LPDDR2接口相比，这些新接口的功耗有5倍。
3D stacking is seen as one of the most interesting technologies for System-on-Chip (SoC) developments. However, 3D technologies using Through Silicon Vias (TSV) have not yet proved their viability for being deployed in large-range of products. In this paper, we are investigating 3D Network-on-Chip has a promising solution for increased modularity and scalability. We show that an efficient implementation based on asynchronous logic provides an available bandwidth of 64GB/s for only 700 TSV, outperforming classical interfaces while simplifying the assembly process. We also point out the benefit in terms of power consumption for these new interfaces with a gain of 5 times compared to classical LPDDR2 interfaces.