Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process
Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process
复制标题
90 nm 双 V/sub T/ CMOS 工艺中耐 SER 锁存器的测量和分析
DOI：
10.1109/jssc.2004.831449
复制
发表时间：
2004
影响因子：
5.4
通讯作者：
S. Borkar
中科院分区：
文献类型：
--
作者：
P. Hazucha;T. Karnik;S. Walstra;B. Bloechel;J. Tschanz;J. Maiz;K. Soumyanath;G. Dermer;S. Narendra;V. De;S. Borkar
我们利用本地冗余设计了一种软错误率（SER）容忍锁存器。我们在 90 nm 双 V/sub T/CMOS 工艺中实现了一个包含标准锁存器和 SER 容限锁存器的测试芯片。洛斯阿拉莫斯国家实验室的中子束加速测量表明，耐 SER 锁存器的可靠性比标准锁存器高出 10/spl 倍，而且速度没有降低。最坏情况下的能源和面积损失分别为 39% 和 44%。对于至少是最小宽度两倍的标准锁存晶体管尺寸来说，能量和面积损失都可以忽略不计。我们分析了恢复时间、阈值电压分配和泄漏对 SER 鲁棒性的影响。所提出的锁存器可以提高微处理器和其他电路中关键时序逻辑元件的可靠性。
We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10/spl times/ better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits.