A Metal-Via Resistance Based Physically Unclonable Function With Backend Incremental ADC
A Metal-Via Resistance Based Physically Unclonable Function With Backend Incremental ADC
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DOI：
10.1109/tcsi.2021.3105907
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发表时间：
2021-11
期刊：
影响因子：
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通讯作者：
Beomsoo Park;Domenic Forte;M. Tehranipoor;N. Maghari
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文献类型：
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作者：
Beomsoo Park;Domenic Forte;M. Tehranipoor;N. Maghari
本文提出了一种用于安全认证的新型物理不可克隆函数（PUF）。它不是利用晶体管的差异或工艺设计套件（PDK）所提供的无源元件作为熵源，而是将金属层和过孔层之间产生的寄生电阻用作静态熵源。由寄生电阻构成的对称电桥结构产生了用于比较的必要电压差。实现了一个精确的后端增量式模数转换器（IADC），用于将电压差转换为数字化值。IADC的操作能够实现良好的本征不稳定性。实现了两种不同类型的布局结构以产生必要的寄生电阻并进行了比较。该原型PUF采用65纳米工艺制造，经过5000次重复评估，其本征不稳定性和误码率分别低于1.45%和0.12%。在不使用任何稳定技术的情况下，所提出的设计在0.9至1.4V的电压范围和0°C至85°C的温度范围内，分别呈现出0.58%/0.1V和0.53%/10°C的误码率。芯片内和芯片间汉明距离之间的距离比高于305倍。
This paper presents a novel physically unclonable function (PUF) for security authentication. Instead of using the variation of transistors or PDK provided passive components as entropy source, the parasitic resistance created between metal and via layers is used as the static entropy source. A symmetric bridge configuration consisted with the parasitic resistance creates the necessary voltage difference for comparison. An accurate backend incremental analog-to-digital converter (IADC) is implemented to convert the voltage difference into a digitized value. The operation of the IADC allows to achieve a good native instability. Two different types of layout structures are implemented to create the necessary parasitic resistance and compared. Fabricated in a 65nm process, the prototype PUF achieves a native instability and bit error rate of less than 1.45% and 0.12% with 5000 repeated evaluations. The proposed design shows 0.58%/0.1V and 0.53%/10°C bit error across the voltage and temperature range of 0.9 to 1.4V and 0°C to 85°C, respectively without any stabilization techniques. The distance ratio between intra-die and inter-die Hamming Distance is above $305\times $ .