Estimation of power dissipation in CMOS combinational circuits
Estimation of power dissipation in CMOS combinational circuits
复制标题
CMOS 组合电路中功耗的估计
DOI：
10.1109/cicc.1990.124782
复制
发表时间：
1990
期刊：
影响因子：
--
通讯作者：
Jacob K. White
中科院分区：
文献类型：
--
作者：
S. Devadas;K. Keutzer;Jacob K. White
结果表明，一个简化的功耗模型将最大化功耗与最大化门输出活动联系在一起，并根据不同的负载电容进行适当的加权。为了找到使加权活动最大化的输入或输入序列，给出了将该问题转化为加权极大可满足性问题的算法，然后给出了求解加权极大可满足性的精确算法和近似算法。也就是说，提出将逻辑描述转换成输入向量或向量序列的多输出布尔函数的变换，其中布尔函数的每个输出与逻辑门输出转换相关联。给出了动态和静态两种情况下考虑毛刺损耗的布尔函数的构造算法。最后，给出了求解所生成的加权极大可满足性问题的有效的精确和近似方法。
It is shown that a simplified model of power dissipation relates maximizing dissipation to maximizing gate output activity, appropriately weighted to account for differing load capacitances. To find the input or input sequence that maximizes the weighted activity, algorithms are given for transforming the problem to a weighted max-satisfiability problem, and then exact and approximate algorithms for solving weighted max-satisfiability are given. That is, transformations are presented that convert a logic description into a multiple-output Boolean function of the input vector or vector sequence, where each output of the Boolean function is associated with a logic gate output transition. Algorithms for constructing the Boolean function for dynamic CMOS and static CMOS, which take into account dissipation due to glitching, are presented. Finally, efficient exact and approximate methods for solving the generated weighted max-satisfiability problem are presented.<<ETX>>