Revisiting automated physical synthesis of high-performance clock networks
Revisiting automated physical synthesis of high-performance clock networks
复制标题
重新审视高性能时钟网络的自动物理综合
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
R. Reis
中科院分区：
文献类型：
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作者：
Matthew R. Guthaus;G. Wilke;R. Reis
近三十年来，高性能时钟分配一直是一项挑战。在此期间，时钟合成工具和算法一直在努力解决无数重要问题，帮助设计人员创建更快、更可靠、更节能的芯片。这项工作提供了一个完整的讨论高性能ASIC时钟分配使用的信息收集从领先的工业时钟设计师和以前的研究出版物。虽然许多技术只是简单地解释，但参考文献总结了各种主题上最有影响力的论文，以便进行更深入的研究。本文还对时钟合成中的当前问题进行了深入讨论，并对整个社区未来的研究和设计挑战进行了深入分析。
High-performance clock distribution has been a challenge for nearly three decades. During this time, clock synthesis tools and algorithms have strove to address a myriad of important issues helping designers to create faster, more reliable, and more power efficient chips. This work provides a complete discussion of the high-performance ASIC clock distribution using information gathered from both leading industrial clock designers and previous research publications. While many techniques are only briefly explained, the references summarize the most influential papers on a variety of topics for more in-depth investigation. This article also provides a thorough discussion of current issues in clock synthesis and concludes with insight into future research and design challenges for the community at large.