BayesPerf: minimizing performance monitoring errors using Bayesian statistics
BayesPerf: minimizing performance monitoring errors using Bayesian statistics
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DOI：
10.1145/3445814.3446739
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发表时间：
2021-02
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通讯作者：
Subho Sankar Banerjee;Saurabh Jha;Z. Kalbarczyk;R. Iyer
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作者：
Subho Sankar Banerjee;Saurabh Jha;Z. Kalbarczyk;R. Iyer
硬件性能计数器（HPC）测量低级架构和微架构事件，提供有关系统状态的动态上下文信息。然而，HPC测量由于非确定性（例如，由于事件多路复用或OS中断处理行为而导致的计数不足）。在本文中，我们提出了BayesPerf，一个系统，用于量化HPC测量的不确定性，通过使用域驱动的贝叶斯模型，捕获HPC之间的微架构关系，共同推断其值的概率分布。我们提供了一个加速器的设计和实现，该加速器允许x86和ppc64 CPU的BayesPerf模型的低延迟和低功耗推理。当事件被多路复用时，BayesPerf将HPC测量的平均误差从40.1%降低到7.6%。BayesPerf在实时决策中的价值通过PCIe传输调度的简单示例来说明。
Hardware performance counters (HPCs) that measure low-level architectural and microarchitectural events provide dynamic contextual information about the state of the system. However, HPC measurements are error-prone due to non determinism (e.g., undercounting due to event multiplexing, or OS interrupt-handling behaviors). In this paper, we present BayesPerf, a system for quantifying uncertainty in HPC measurements by using a domain-driven Bayesian model that captures microarchitectural relationships between HPCs to jointly infer their values as probability distributions. We provide the design and implementation of an accelerator that allows for low-latency and low-power inference of the BayesPerf model for x86 and ppc64 CPUs. BayesPerf reduces the average error in HPC measurements from 40.1% to 7.6% when events are being multiplexed. The value of BayesPerf in real-time decision-making is illustrated with a simple example of scheduling of PCIe transfers.