(Invited) Transistor application using vertical III-V nanowires on Si platform
(Invited) Transistor application using vertical III-V nanowires on Si platform
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（特邀）Si平台上垂直III-V纳米线的晶体管应用
DOI：
10.1149/08001.0043ecst
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发表时间：
2017
期刊：
影响因子：
--
通讯作者：
Katsuhiro Tomioka and Takashi Fukui
中科院分区：
文献类型：
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作者：
W. Zhang;S. Netsu;T. Kanazawa;T. Amemiya;Y. Miyamoto;Katsuhiro Tomioka and Takashi Fukui
垂直III-V族纳米线（NW）是用于未来集成电路中的高速开关器件的有前途的沟道材料，因为环绕栅极结构具有良好的静电栅极可控性，同时抑制III-V族沟道中固有的大泄漏电流，并且在功耗方面优于横向开关器件，同时保持良好的可扩展性。至于在Si上集成III-V纳米线，由于位置/尺寸均匀性和具有调制掺杂的核-壳结构，通过选择性区域生长的垂直III-V纳米线的直接集成对于高性能晶体管应用具有优势。
Vertical III-V nanowire (NW) is a promising channel material for high-speed switching devices in future integrated circuits because surrounding-gate structures have good electrostatic gate controllability while suppressing inherent large leakage current in III-V channels and outperform lateral switching devices in terms of power consumption while keeping good scalability. As for the integration of III-V NWs on Si, direct integration of vertical III-V NWs by selective-area growth has advantages for highperformance transistor applications because of position/sizeuniformity and core-shell structure with modulation doping.