A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS
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DOI：
10.1109/asscc.2015.7387448
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发表时间：
2015-11
期刊：
影响因子：
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通讯作者：
W. Bae;Haram Ju;Kwanseo Park;Sung-Yong Cho;D. Jeong
中科院分区：
文献类型：
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作者：
W. Bae;Haram Ju;Kwanseo Park;Sung-Yong Cho;D. Jeong
This paper presents a -245.3 dB FoMJ phase-locked loop based on a ring oscillator and a novel analysis on 2-stage ring oscillator. The proposed PLL generates a 4-phase 10-GHz clock for a 40-Gb/s serial link transmitter. The proposed analysis offers a time-domain insight on 2-stage ring oscillator and a precise prediction on oscillator behavior such as an output frequency and whether the 2-stage ring oscillates or not, based on a simple open-loop approach with a single stage buffer. The prototype chip is fabricated in 65-nm CMOS technology, and the PLL occupies only 0.009 mm2 and dissipates 7.6 mW from 1.2-V supply and 9 mW from 1.3-V supply. The measured integrated jitter of the PLL is 214 fs from 1.2-V supply and 182 fs from 1.3-V supply, which corresponds to -244.6 dB and -245.3 dB FoMJ, respectively.
