Framework of timed trace theoretic verification revisited
Framework of timed trace theoretic verification revisited
复制标题
重新审视定时轨迹理论验证框架
DOI：
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
C. Myers
中科院分区：
文献类型：
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作者：
Bin Zhou;T. Yoneda;C. Myers
针对异步电路的形式化验证问题，提出了一个支持时序电路和系统迹论验证的框架。发展了一种将定时跟踪分类为成功或失败的理论基础。半镜的概念被引入到允许一致性检查，从而支持分层验证的定时电路和系统。最后，我们将我们的框架与以前提出的时间验证。
For the formal verification of asynchronous circuits, a framework to support trace theoretic verification of timed circuits and systems was developed. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.