Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems 1 Simulate and Eliminate: a Top-to-bottom Design Methodology for Automatic Generation of Application Specific Architectures
Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems 1 Simulate and Eliminate: a Top-to-bottom Design Methodology for Automatic Generation of Application Specific Architectures
复制标题
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 1 模拟和消除：自动生成特定应用架构的自顶向下设计方法
DOI：
--
复制
发表时间：
--
期刊：
影响因子：
--
通讯作者：
R. Kastner
中科院分区：
文献类型：
--
作者：
A. Irturk;J. Matai;J. Oberg;Jeffrey Su;R. Kastner
—应用程序特定处理的趋势日益明显，特别是在具有严格性能要求的嵌入式计算设备中。实现所需的面积和吞吐量限制需要仔细调整底层架构，并且高级设计工具正在获得越来越多的认可，以实现这一目标，同时减少设计时间。大多数现有工具采用自下而上的方法，根据给定的应用程序将功能单元、互连和控制逻辑组合在一起；这往往扩展性很差。我们开发了一种模拟和消除（S&E）工具，它与现有的高级设计工具有根本的不同，因为它采用了自上而下的方法。 S&E 提供自动生成各种具有不同参数化选项的通用处理核心。然后，在该通用架构上模拟所提供的应用程序，并消除不需要的功能，从而形成应用程序特定架构。 S&E 为输入 C 和/或 MATLAB 代码生成完全可综合的硬件描述语言。 S&E 提供不同的设计方法和参数化选项，使用户能够研究大量不同架构的面积和性能权衡，并找到实现所需目标的最佳架构。
—There is an increasing trend toward application specific processing, particularly in embedded computing devices that have stringent performance requirements. Achieving the desired area and throughput constraints requires careful tuning of the underlying architecture and high-level design tools are gaining increasing acceptance to achieve this goal while decreasing the design time. Most existing tools employ a bottom-to-top methodology, which piece together functional units, interconnect, and control logic based on the given application; this tends to scale poorly. We developed a tool, simulate and eliminate (S&E), that is fundamentally different from the existing high-level design tools as it employs a top-to-bottom methodology. S&E provides automatic generation of a variety of general purpose processing cores with different parameterization options. Then, the provided application(s) are simulated on this general-purpose architecture and the unneeded functionality is eliminated resulting in application specific architecture. S&E generates completely synthesizable hardware description language for an input C and/or MATLAB code. S&E provides different design methods and parameteriza-tion options to enable the user to study area and performance tradeoffs over a large number of different architectures and find the optimum architecture for the desired objective.