Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking
Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking
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DOI：
10.1145/3453688.3461508
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发表时间：
2021-06
期刊：
影响因子：
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通讯作者：
Zhiming Zhang;Ivan Miketic;E. Salman;Qiaoyan Yu
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文献类型：
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作者：
Zhiming Zhang;Ivan Miketic;E. Salman;Qiaoyan Yu
逻辑锁定已证明其在保护集成电路 (IC) 知识产权方面的潜力。逻辑锁定的安全强度通常通过基于功能和结构分析的攻击来评估。分析逻辑锁定技术抵御基于功率的旁道攻击的能力的工作有限。为了填补这一空白，我们提出了一种针对晶体管级逻辑锁定加密电路的相关功率分析（CPA）攻击的攻击流程。我们的案例研究表明，CPA 攻击在密钥恢复率 (KRR) 方面优于 DPA 攻击。为了提高现有晶体管级逻辑锁定技术的CPA攻击弹性，我们提出了一种逻辑锥结合（LCC）方法来扩大密钥空间并减少锁定密钥与锁定电路功耗之间的相关性。实验结果表明，LCC方法通过使用循环逻辑结构成功地将KRR从100%降低到0%。 FPGA 仿真表明，与基线相比，所提出的方法延迟增加了 2.6%，功耗增加了 1.5%。
Logic locking has demonstrated its potential to protect the intellectual property of integrated circuits (ICs). The security strength of logic locking is typically evaluated through functional and structural analysis-based attacks. There is limited work analyzing logic locking techniques' resilience against power-based side-channel attacks. To fill this gap, we propose an attack flow for the correlation power analysis (CPA) attack on the circuits encrypted with transistor-level logic locking. Our case studies indicate that CPA attacks outperform DPA attacks in terms of key recovery rate (KRR). To improve the CPA attack resilience of an existing transistor-level logic locking technique, we propose a logic-cone conjunction (LCC) method to enlarge the key space and reduce the correlation between the locking key and the power consumption of locked circuits. The experimental results show that the LCC method successfully reduces the KRR from 100% to 0% by using cyclic logic structures. The FPGA emulation indicates that the proposed method incurs 2.6% more delay and 1.5% more power consumption than the baseline.