Dual-edge triggered static pulsed flip-flops
Dual-edge triggered static pulsed flip-flops
复制标题
双边沿触发静态脉冲触发器
DOI：
10.1109/icvd.2005.84
复制
发表时间：
2005
期刊：
影响因子：
--
通讯作者：
H. Mahmoodi
中科院分区：
文献类型：
--
作者：
A. Ghadiri;H. Mahmoodi
本文提出了两种结构简单的低功耗双边沿触发静态脉冲触发器（DSPFF）。它们由一个双边沿脉冲发生器和一个具有相等触发延迟的静态触发器组成。DSPFF的静态特性避免了不必要的内部节点转换，以降低功耗。提出了一种结构简单的双边沿触发脉冲发生器，可降低时钟分配网络的功耗。DSPFF的功耗被认为是所有高性能触发器和锁存器中最低的。HSPICE仿真结果表明，在400 MHz的频率下，建议的DSPFF表现出超过24%的PDP减少相比，混合锁存触发器（HLFF）和超过14%的PDP减少相比，条件捕获触发器（CCFF）。在实际电路中，与HLFF相比，DSPFF的功耗降低了64%，与CCFF相比，DSPFF的功耗降低了59%。
Two simple structures of low-power dual-edge triggered static pulsed flip-flops (DSPFF) are presented in this paper. They are composed of a dual-edge pulse generator and a static flip-flop with equal toggling delays. The static feature of DSPFF avoids unnecessary internal node transitions to reduce power consumption. Simple structure of pulse generator with double-edge triggering is proposed that results in low power dissipation in clock distribution networks. Power consumption of the DSPFF is observed to be the lowest among all high-performance flip-flops and latches. HSPICE simulation results at a frequency of 400 MHz show that the proposed DSPFF exhibits more than 24% PDP reduction compared to the hybrid-latch flip-flop (HLFF) and more than 14% PDP reduction compared to conditional-capture flip-flop (CCFF). The proposed DSPFF shows 64% power reduction in comparison to the HLFF and 59% power reduction in comparison to CCFF in practical circuits.