A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters
A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters
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DOI：
10.1109/nano54668.2022.9928674
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发表时间：
2022-07
期刊：
影响因子：
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通讯作者：
Aibin Yan;Shukai Song;Yu Chen;Jie Cui;Zhengfeng Huang;X. Wen
中科院分区：
文献类型：
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作者：
Aibin Yan;Shukai Song;Yu Chen;Jie Cui;Zhengfeng Huang;X. Wen
本文提出了一种新的低成本和鲁棒的锁存器，即LRLPT，防止三节点翻转（TNUs）的纳米级CMOS。锁存器的存储部分包括互锁的源极-漏极交叉耦合的反相器，其形成冗余反馈回路以稳健地存储值。仿真结果证明了该锁存器的所有关键TNU的恢复。仿真结果还表明，所提出的锁存器可以节省69.67%的延迟，37.51%的硅面积和71.77%的延迟面积功率积（DAPP）相比，最先进的TNU恢复参考锁存器的相同类型。
This paper proposes a novel low-cost and robust latch, namely LRLPT, protected against triple-node upsets (TNUs) in nano-scale CMOS. The storage part of the latch comprises interlocked source-drain cross-coupled inverters forming redundant feedback loops to robustly store values. Simulation results demonstrate all key TNUs' recovery of the proposed latch. Simulation results also demonstrate that the proposed latch can save 69.67% delay, 37.51% silicon area and 71.77% delay-area-power product (DAPP) compared to the state-of-the-art TNU-recovery reference latch of the same-type.