The Multiple Wordlength Paradigm
The Multiple Wordlength Paradigm
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多字长范例
DOI：
10.1109/fccm.2001.46
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
W. Luk
中科院分区：
文献类型：
--
作者：
G. Constantinides;P. Cheung;W. Luk
本文为设计DSP框图中每个信号的单词lorggength和缩放的DSP应用程序设计了多个WordLength并行处理系统的设计范式。说明了一种用于估计截断和圆形误差的可观察效应的技术，并用于构成优化算法的基础，以自动化此类多个WordLength系统的设计。可重新配置计算平台上实现的结果表明，可以通过根据本文所述的技术自定义DataPath Precision来自定义DataPath Precision来获得大量逻辑使用率和增加的时钟速率。在选定的DSP基准测试中，我们最多可获得45％的面积和高达39％的速度，而速度比标准设计技术提高了39％。
This paper presents a paradigm for the design of multiple wordlength parallel processing systems for DSP applications based on varying the wordlength and scaling of each signal in a DSP block diagram. A technique for estimating the observable effects of truncation and roundoff error is illustrated, and used to form the basis of an optimization algorithm to automate the design of such multiple wordlength systems. Results from implementation on a reconfigurable computing platform show that significant logic usage savings and increased clock rates can be obtained by customizing the datapath precision to the algorithm according to the techniques described in this paper. On selected DSP benchmarks, we obtain up to 45% area reduction and up to 39% speed increase over standard design techniques.