Product-representative 'at speed' test structures for CMOS characterization
Product-representative 'at speed' test structures for CMOS characterization
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用于 CMOS 表征的产品代表性“快速”测试结构
DOI：
10.1147/rd.504.0451
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
M. Bhushan
中科院分区：
文献类型：
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作者：
M. Ketchen;M. Bhushan
描述了用于测量和表征CMOS电路性能、功率和当今微处理器速度特性变化的产品代表性测试结构的设计。目前在IBM部分耗尽绝缘体上硅CMOS技术中使用的这组测试结构包括早期工艺开发中的诊断、监控制造中的成熟工艺、实现模型与硬件的关联以及跟踪产品性能。该设计专注于在产品制造周期的早期测量高频性能，同时最大限度地减少测试和数据分析时间。物理布局紧凑，便于在芯片中放置。这些测试结构的子集可以在第一金属层进行测量，而更复杂的设计则使用三层或更多的金属层。大多数设计与标准在线参数测试设备兼容，尽管有限数量的台架测试继续发挥重要作用。差分测量技术是许多测试结构设计的关键。硬件数据分析还严重依赖于差分方案，用于以自洽的方式将MOSFET参数和相关寄生组件与电路延迟相关联。
The design of product-representative test structures for measuring and characterizing CMOS circuit performance, power, and variability at speeds characteristic of present-day microprocessors is described. The current use of this set of test structures in the IBM partially depleted silicon-on-insulator CMOS technologies covers diagnostics in early process development, monitoring mature processes in manufacturing, enabling model-to-hardware correlation, and tracking product performance. The designs focus on measuring high-frequency performance early in the product fabrication cycle while minimizing test and data analysis time. The physical layouts are compact, facilitating placement in the chip. A subset of these test structures can be measured at the first metal level, while more complex designs use three or more metal layers. Most designs are compatible with standard in-line parametric test equipment, although a limited number of bench tests continue to play an important role. Differential measurement techniques are key to many of the test structure designs. Hardware data analysis also relies heavily on differencing schemes for relating MOSFET parameters and associated parasitic components to circuit delays in a self-consistent manner.