Calculational derivation of a counter with bounded response time and bounded power dissipation

Calculational derivation of a counter with bounded response time and bounded power dissipation
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具有有限响应时间和有限功耗的计数器的计算推导

DOI:
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发表时间:
1995
影响因子:
1.3
通讯作者:
J. Kessels
J. Kessels
中科院分区:
计算机科学3区
文献类型:
--
作者:
J. Kessels

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摘要计数器是通过应用函数式编程方法进行计算设计的,在该程序中,机器被设想为从状态到行为的函数。该设计利用了VLSI中可用的细粒度并发。它是通过对满足功能规范但不满足性价比要求的初始设计进行一系列保持正确性的变换而得到的。这些转换纯粹是计算的,也就是说,它们是基于一些简单的公理。该设计是通用的,因为它描述了具有所有可能周期的计数器。该设计的一个吸引人的特性是所有这些计数器都具有相同的响应时间和相同的功耗。
SummaryA counter is calculationally designed by applying a functional way of programming, in which a machine is conceived as a function from states to behaviours. The design exploits the fine-grained concurrency available in VLSI. It is obtained by applying a series of correctness-preserving transformations on an initial design, which satisfies the functional specification but does not meet the cost/performance requirements. The transformations are purely calculational, i.e. they are based on a few simple axioms. The design is generic in that it describes counters with all possible periods. An attractive property of the design is that all these counters have the same response time as well as the same power dissipation.