Deep sub-micron chip development
Deep sub-micron chip development
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深亚微米芯片开发
DOI：
10.1016/j.nima.2006.09.021
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发表时间：
2006
影响因子：
1.4
通讯作者：
H. Ikeda
中科院分区：
文献类型：
--
作者：
H. Ikeda
通过相关大学和研究机构的共同努力，在多芯片项目服务下，深亚微米CMOS工艺的应用正在迅速扩散。为了弥补设计人员资源的不足，已经组织了亚微米CMOS工艺电路库，供业余设计人员使用。在实践中，这些库被用于几个项目，因此，这些库本身逐渐变得更加复杂，甚至可以用于最近的制造工艺，如深亚微米FD-SOI CMOS工艺。设计并提出了SOI CMOS工艺的测试电路，以检验其在辐射探测器前端模拟电路中的性能和实用性。
The application of a deep sub-micron CMOS process is rapidly being proliferated under a multi-chip project service through the joint efforts of related universities and research organizations. In order to compensate for the shortage in designer resources, circuit libraries of sub-micron CMOS processes have been organized to be used by amateur designers. In practice, the libraries are employed in several projects, and, thus, the libraries themselves gradually become more sophisticated to the extent of even being utilized for very recent fabrication processes such as a deep sub-micron FD-SOI CMOS process. A test circuit for the SOI CMOS process is designed and submitted to examine its performance and usefulness in a front-end analog circuit of radiation detectors.