Traffic-aware power-gating scheme for Network-on-Chip routers
Traffic-aware power-gating scheme for Network-on-Chip routers
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DOI：
10.1109/dcas.2016.7791134
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发表时间：
2016-10
期刊：
影响因子：
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通讯作者：
N. Nasirian;Reza Soosahabi;M. Bayoumi
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文献类型：
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作者：
N. Nasirian;Reza Soosahabi;M. Bayoumi
近十年来，片上网络技术已经成为解决多核处理器可伸缩性问题的热门技术。开发互连网络提高了多核系统的性能，但代价是增加了功率和设计复杂性。作为片上网络中功耗最大的部分，路由器缓冲器的功耗门控是最近提出的一种降低静态功耗的方法。然而，功率门控在延迟和功率开销方面有其自身的缺点，如果不与流量同步使用，可能会降低整体性能。本文引入了一种功率管理技术来优化路由器输入缓冲器的功率门控，利用一种自适应学习方案来估计未来的流量到达。所提出的设计基于业务到达间隔时间的统计估计，智能地将功率门控信号调用到路由器缓冲器。将功率门控信号与业务到达同步显著地减少了由以下原因引起的功率门控开销：路由立即业务到达的强制唤醒延迟以及由于预期未来到达而延长空闲状态而导致的静态功率消耗。仿真结果表明，与以往的工作相比，该方案的静态功耗平均提高了25%，而分组平均时延与朴素功率门控相比降低了35%。值得一提的是，与文献[1]中提出的方案相比，功率门控的开销显著降低了41%。
Network-on-Chip technology has become very popular in the recent decade to address the scalability issue in multi-core processors. Developing the inter-connection network improves the performance of multi-core systems at the cost of additional power and design complexity. Power-gating of router buffers as the most power consuming part of Network-on-Chip has been proposed recently to reduce the static power consumption. However, power-gating has its own shortcomings in terms of delay and power overhead that can diminish the overall performance if it is not used in sync with the traffic flow. In this paper, a power management technique has been introduced to optimize the power-gating of router input buffers by utilizing an adaptive learning scheme to estimate the future traffic arrival. The proposed design intelligently invokes the power-gating signals to the router buffers based on the statistical estimation of the traffic inter-arrival times. Syncing the power-gating signals with the traffic arrival significantly reduces the power-gating overhead caused by: mandatory wake-up delay to route immediate traffic arrival and static power consumption due to prolonging idle state in anticipation of future arrival. The simulation results indicate that the proposed scheme has average 25% improvement in the static power consumption compared to previous works while it reduces the average packet latency by 35% in comparison to naive power-gating. It is worth mentioning that the overhead of power-gating has significantly decreased by 41% compared to the proposed scheme in [1].