DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining
DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining
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DRAMbulism：通过动态流水线平衡性能和可预测性
DOI：
10.1109/rtas48715.2020.00-15
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发表时间：
2020
期刊：
影响因子：
--
通讯作者：
R. Pellizzoni
中科院分区：
文献类型：
--
作者：
Reza Mirosanlou;Mohamed Hassan;R. Pellizzoni
实时程序的最坏情况执行边界受到访问硬件共享资源（如片外DRAM）的延迟的深刻影响。虽然在文献中已经提出了许多不同的存储器控制器设计，但在平均情况性能和可预测的最坏情况界限之间存在权衡，因为针对改善前者的技术可能会损害后者，反之亦然。我们发现，利用不同的命令之间的流水线可以改善这两个，但在最坏情况下的分析，结合流水线的影响是具有挑战性的。在这项工作中，我们介绍了一种新的DRAM控制器，成功地平衡性能和可预测性，采用动态流水线方案。我们表明，DRAM命令的时间表是类似于一个两阶段的两种模式的管道，因此，设计一个易于实现的准入规则，使我们能够动态地添加请求的管道，而不会伤害最坏情况下的界限。
Worst-case execution bounds for real-time programs are profoundly impacted by the latency of accessing hardware shared resources, such as off-chip DRAM. While many different memory controller designs have been proposed in the literature, there is a trade-off between average-case performance and predictable worst-case bounds, as techniques targeted at improving the former can harm the latter and vice-versa. We find that taking advantage of pipelining between different commands can improve both, but incorporating pipelining effects in worst-case analysis is challenging. In this work, we introduce a novel DRAM controller that successfully balances performance and predictability by employing a dynamic pipelining scheme. We show that the schedule of DRAM commands is akin to a two-stage two-mode pipeline, and hence, design an easily-implementable admission rule that allows us to dynamically add requests to the pipeline without hurting worst-case bounds.
在现代异构 MPSoC 平台上设计混合关键应用
DOI：
10.4230/lipics.ecrts.2019.27
发表时间：
2019
期刊：
Euromicro Conference on Real-Time Systems (ECRTS 2019
影响因子：
--
作者：
Gracioli, Giovani;Tabish, Rohan;Mancuso, Renato;Mirosanlou, Reza;Pellizzoni, Rodolfo;Caccamo, Marco
通讯作者：
Caccamo, Marco