Compact and Low Power Analog Front End with in-situ Data Decimator for High-Channel-Count ECoG Recording
Compact and Low Power Analog Front End with in-situ Data Decimator for High-Channel-Count ECoG Recording
复制标题
紧凑型低功耗模拟前端，具有用于高通道数 ECoG 记录的原位数据抽取器
DOI：
10.1109/iscas.2018.8351245
复制
发表时间：
2018
期刊：
影响因子：
--
通讯作者：
A. Mason
中科院分区：
文献类型：
--
作者：
E. Ashoori;Sylmarie Dávila;A. Mason
高通道数神经植入物可以记录不同皮层区域的大脑活动，代表了迈向全脑接口的下一步，这将使人们对大脑运作和许多神经疾病的治疗有新的理解。为了克服现有神经植入物的尺寸和功率限制的通道数，本文提出了一种新的神经放大器阵列设计，利用硬件共享，以实现低功耗和紧凑的尺寸。此外，为了减轻大量数据处理的负担，执行原位数据抽取以实现信号对之间的同步的离体评估。设计了一个32通道的模拟前端阵列，版图后仿真表明，在0.5 μ mCMOS芯片上，在3.3V电压下，整个前端每通道占用面积仅为0.031mm2，每通道功耗仅为3.34 μW。该前端将数据抽取一个数量级，同时保持同步信息的准确率超过89.1%。
High channel count neural implants that can record brain activities across diverse cortical regions represent the next step toward whole brain interfaces that will enable new understanding of brain operation and treatment of many neural disorders. To overcome the size and power constraints limiting the channel count of existing neural implants, this paper presents a new neural amplifier array design that utilizes hardware sharing to achieve low power and compact size. Moreover, to ease the burden of large volume data handling, in-situ data decimation is performed to enable off body evaluation of synchrony between signal pairs. A 32-channel analog front end array was designed and post-layout simulations show that the entire front end occupies only 0.031 mm2 per channel while consuming only 3.34 μW per channel at 3.3 V in 0.5 μm CMOS. This front end decimates data by an order of magnitude while keeping the synchrony information with more than 89.1% accuracy.