Aggressively scaled high-k last metal gate stack with low variability for 20nm logic high performance and low power applications

Aggressively scaled high-k last metal gate stack with low variability for 20nm logic high performance and low power applications
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发表时间:
2011-06
期刊:
2011 Symposium on VLSI Technology - Digest of Technical Papers
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通讯作者:
S. Hyun;J.-H. Han;H.B. Park;H.-J. Na;H. Son;H. Lee;Heebum Hong;H. Lee;J. Song;J.J. Kim
S. Hyun;J.-H. Han;H.B. Park;H.-J. Na;H. Son;H. Lee;Heebum Hong;H. Lee;J. Song;J.J. Kim
中科院分区:
其他
文献类型:
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作者:
S. Hyun;J.-H. Han;H.B. Park;H.-J. Na;H. Son;H. Lee;Heebum Hong;H. Lee;J. Song;J.J. Kim

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一种大规模的高k末金属栅极(HKMG)堆叠成功实现了20nm高性能和低功耗应用,甚至更低。关键技术包括利用新HK将Tinv缩小到1.1nm,抑制Vfb滚降,金属层控制Vt及其优异的均匀性,以及金属栅应力工程以提高性能。
An aggressively scaled high-k last metal gate (HKMG) stack was successfully implemented for 20nm high performance and low power applications and even below. Key technologies include aggressive Tinv scaling down to 1.1nm with new HK, suppression of Vfb roll-off, metal layer control for Vt and its excellent uniformity, and metal gate stress engineering for performance improvement.