Adaptive hardware by dynamic reconfiguration for the Solar Orbiter PHI instrument
Adaptive hardware by dynamic reconfiguration for the Solar Orbiter PHI instrument
复制标题
通过动态重新配置太阳轨道器 PHI 仪器的自适应硬件
DOI：
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发表时间：
2012
期刊：
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通讯作者：
J. Hirzberger
中科院分区：
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作者：
B. Fiethe;F. Bubenhagen;T. Lange;H. Michalik;Holger Michel;J. Woch;J. Hirzberger
由于遥测速率有限，再加上从太阳轨道器上的偏振和日震成像仪的照相机系统中检索到大量科学信息，因此需要在卫星上进行确定科学参数等传统的地面处理步骤。具有大逻辑密度的现场可编程门阵列（FPGA）提供了高度灵活的平台来实现此类复杂的功能。具体而言，基于SRAM的FPGA的抗辐射空间适用性显著提高了空间应用高可靠系统的灵活性，并已在许多空间任务中得到验证。此外，基于SRAM的FPGA支持动态（部分）重新配置的潜力允许以时空划分（TSP）方式灵活使用可用硬件（HW）平台。对于PHI数据处理单元（DPU），这些FPGA的无缝可重新配置性使FPGA资源能够在不同的操作模式下多次使用，即一种专用配置用于图像采集，另一种配置用于后续数据处理。其他的优点，如增强系统的灵活性或在飞行中适应不断变化的使命的要求。为PHI DPU设计提出的基本结构是基于ESA对动态可重构处理模块（DRPM）的研究结果。通信架构采用我们自己的SpaceWire基于片上系统线（SoCWire），这是能够连接可重构模块到主机系统的能力，以隔离这些模块的逻辑和物理。为了安全的飞行中更新，从地面上传直到存储在配置存储器中，必须保证上传的硬件代码的数据完整性，以保持系统合格。考虑到配置存储器中可能的单粒子翻转（SEU）错误，这一点尤其重要。一个合理的分离所需的功能模块在不同的配置的FPGA。FPGA的必要重新配置对操作没有影响。最后，所需资源的比较总结清楚地概述了动态可重构配置的优点，从而降低使命成本。
A limited telemetry rate combined with a large amount of scientific information retrieved from the camera systems of the Polarimetric and Helioseismic Imager (PHI) instrument on Solar Orbiter demand that classical ground processing steps like determination of scientific parameters need to be performed already on-board. Field-Programmable Gate Arrays (FPGAs) with large logic density provide a highly flexible platform to implement such sophisticated capabilities. Specifically, radiation tolerant space suitable SRAM-based FPGAs have significantly improved flexibility of high reliable systems for space applications and have already been proven in many space missions. Furthermore, the potential of SRAM-based FPGAs to support dynamic (partial) reconfiguration allows a flexible use of the available hardware (HW) platform in a TimeSpace Partitioning (TSP) manner. For the PHI Data Processing Unit (DPU), the seamless reconfigurability of these FPGAs enables multiple use of the FPGA resources during different modes of operation, i.e. one dedicated configuration for image acquisition and a different configuration for subsequent data processing. Other advantages like enhanced flexibility of a system or in-flight adaptation to changing mission requirements are presented. The basic structure proposed for the PHI DPU design is based on the results of the ESA study for a Dynamically Reconfigurable Processing Module (DRPM). The communication architecture employs our own SpaceWire based System-on-Chip Wire (SoCWire), which is able to connect reconfigurable modules to a host system with the capability to isolate these modules logically and physically. For safe in-flight update data integrity of the uploaded HW code must be guaranteed from ground upload until storage in configuration memory to maintain system qualification. This is taken into account especially in view of possible Single Event Upsets (SEUs) errors in configuration memory. A reasonable separation of the required functional modules in different configurations for the FPGAs is shown. The necessary reconfiguration of the FPGAs has no operational impact. Finally, a comparative summary of needed resources clearly outlines the advantages of a dynamically reconfigurable configuration, resulting in mission cost reduction.