A Comparison of Defect Models for Fault Location with Iddq Measurements
A Comparison of Defect Models for Fault Location with Iddq Measurements
复制标题
用于故障定位的缺陷模型与 Iddq 测量的比较
DOI：
10.1109/test.1992.527900
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发表时间：
1992
期刊：
影响因子：
--
通讯作者：
R. Aitken
中科院分区：
文献类型：
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作者：
R. Aitken
Iddq测试是测量静态CMOS电路各种状态下的静态电流，已成为一种有用的故障检测技术。在本文中，它示出的Iddq测试可用于精确诊断的缺陷，使用门间和门内短路故障模型。这些模型的效果进行了比较，使用芯片从一个标准的单元ASIC运行。在样本中的151个部分中，已对其中135个部分进行了诊断。在许多这些情况下，预测的缺陷被限制在一个单一的标准电池。
Iddq testing, where quiescent current is measured for a variety of states in static CMOS circuits, has emerged as a useful fault detection technique. In this paper it is shown that Iddq tests may be used for precise diagnosis of defects, using both inter and intra-gate shorts as fault models. The effects of these models are compared, using chips from a standard cell ASIC run. Of the 151 parts in the sample, diagnoses have been obtained for 135 of them. In many of these cases, the predicted defects are confined to a single standard cell.