Unraveling Quantum Annealers using Classical Hardness.

Unraveling Quantum Annealers using Classical Hardness.
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DOI:
10.1038/srep15324
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发表时间:
2015-10-20
期刊:
影响因子:
4.6
通讯作者:
Hen I
Hen I
中科院分区:
综合性期刊3区
文献类型:
--
作者:
Martin-Mayor V;Hen I

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量子技术的最新进展导致了包含数百个量子比特的实验性可编程量子退火优化器的开发和制造。这些优化器通常被称为“D-Wave”芯片,有望比传统的“经典”计算机更快地解决实际的优化问题。量化这些芯片的量子性质的尝试既令人兴奋,也受到怀疑,但也提出了许多关于实验量子退火炉与经典热对口物的区别的基本问题。受最近自旋玻璃理论结果的启发,该理论认为“温度混沌”是导致硬优化问题计算难解性的潜在机制,我们设计了一种通用方法来量化量子退火炉在不同程度温度混沌的优化问题上的性能:量子退火炉在这些问题上优于经典算法的性能可能暗示了量子效应在提供加速方面所起的作用。我们利用我们的方法对D-Wave 2芯片在不同温度混沌问题上的实验研究,并发现,令人惊讶的是,与几种类似的经典算法相比,它的性能尺度不利。我们检测、量化并讨论了几种可能掩盖芯片量子行为的纯经典效应。
Recent advances in quantum technology have led to the development and manufacturing of experimental programmable quantum annealing optimizers that contain hundreds of quantum bits. These optimizers, commonly referred to as ‘D-Wave’ chips, promise to solve practical optimization problems potentially faster than conventional ‘classical’ computers. Attempts to quantify the quantum nature of these chips have been met with both excitement and skepticism but have also brought up numerous fundamental questions pertaining to the distinguishability of experimental quantum annealers from their classical thermal counterparts. Inspired by recent results in spin-glass theory that recognize ‘temperature chaos’ as the underlying mechanism responsible for the computational intractability of hard optimization problems, we devise a general method to quantify the performance of quantum annealers on optimization problems suffering from varying degrees of temperature chaos: A superior performance of quantum annealers over classical algorithms on these may allude to the role that quantum effects play in providing speedup. We utilize our method to experimentally study the D-Wave Two chip on different temperature-chaotic problems and find, surprisingly, that its performance scales unfavorably as compared to several analogous classical algorithms. We detect, quantify and discuss several purely classical effects that possibly mask the quantum behavior of the chip.