Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
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DOI：
10.1016/j.mee.2019.111009
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发表时间：
2019-07-15
影响因子：
2.3
通讯作者：
Lanuzza, Marco
中科院分区：
文献类型：
--
作者：
Garzon, Esteban;De Rose, Raffaele;Lanuzza, Marco
本文研究了基于纳米尺度垂直磁性隧道结和FinFET技术的自旋转移矩磁性随机存取存储器（SIT-MRAM）的工艺可扩展性。我们的研究是在不同的抽象层次上进行的，从器件级到架构级，通过对单个存储器位单元的电路级分析。针对512 KB高速缓存存储器获得的模拟结果表明，从28纳米到20纳米技术节点的扩展导致写入延迟降低（-20%），写入（-36%）和读取（-29%）访问下的能耗降低，同时还确保了几乎两倍的集成密度。这是以略微降低的感测裕度和更高的读取延迟（± 5%）以及由于降低的MTJ热稳定性而导致的数据保持能力的劣化为代价的。
This paper deals with the technology scalability of spin-transfer torque magnetic RAMS (SIT-MRAMs) based on nanoscaled perpendicular magnetic tunnel junctions (MTJs) and FinFET technology. Our study was performed at different levels of abstraction, from device- up to architecture-level passing through a circuit-level analysis for the single memory bitcell. Simulation results obtained for a 512 KB cache memory show that scaling from the 28-nm down to the 20-nm technology node leads to reduced write latency (- 20%) and lower energy consumption under both write (- 36%) and read (- 29%) accesses, while also ensuring an almost doubled integration density. This occurs at the expense of slightly reduced sensing margins and higher read latency ( + 5%), and of a degradation in the data retention capability owing to the reduced MTJ thermal stability.