Testing for floating gates defects in CMOS circuits
Testing for floating gates defects in CMOS circuits
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CMOS 电路中浮栅缺陷的测试
DOI：
10.1109/ats.1998.741618
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发表时间：
1998
期刊：
影响因子：
--
通讯作者：
M. Renovell
中科院分区：
文献类型：
--
作者：
S. Rafiq;A. Ivanov;S. Tabatabaei;M. Renovell
本文研究了经典的静态电压、动态电压和静态电流策略对MOS浮栅晶体管故障的可检测性。缺陷的行为取决于两类参数：可预测参数和不可预测参数。浮栅故障可能导致逻辑值异常、额外延迟或电源电流增加。因此，传统的测试策略只能针对给定范围的不可预测参数检测浮栅故障。这里提出了一种新的测试方案，它允许相当大的电流在稳定状态下流动，使具有浮栅I/SUB DDQ/可测试的电路成为可测试的。结果表明，电压和电流检测的结合可以确保100%检测浮栅缺陷，即不考虑不可预测的参数。分析表明，随着浮栅晶体管初始电荷的增加，电压测试策略的检测间隔变小，而静态电流策略的检测间隔增加。
This paper studies the detectability of MOS floating gate transistor faults considering classical static voltage, dynamic voltage and static current strategies. The behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters. A floating gate fault can induce abnormal logic values, additional delays, or increased power supply current. Consequently, classical test strategies can only detect floating gate faults for a given range of the unpredictable parameter. Here, a new test scheme is proposed, which allows a considerable current to flow in the stable state making the circuit with a floating gate I/sub DDQ/ testable. It is shown that a combination of voltage and current testing can ensure 100% detection of the floating gate defects, i.e., regardless of the unpredictable parameters. Analysis with increasing initial charge on the floating gate transistor shows how the detectability intervals become smaller for the voltage testing strategies and increase for the static current strategy.