Physical Attack Protection Techniques for IC Chip Level Hardware Security
Physical Attack Protection Techniques for IC Chip Level Hardware Security
复制标题
IC芯片级硬件安全的物理攻击防护技术
DOI：
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复制
发表时间：
2021
影响因子：
2.8
通讯作者：
N. Miura
中科院分区：
文献类型：
--
作者：
M. Nagata;Takuji Miki;N. Miura
在实际应用环境中，对集成电路（IC）芯片的恶意攻击对安全硬件系统构成了威胁。本文概述了对加密电路的物理攻击、IC芯片中的相关漏洞以及系统、电路和封装技术垂直统一中的保护方案。讨论了传感攻击者企图的片上监控电路的设计原理，并用Si演示器进行了测试。探索了安全IC芯片的物理结构，以建立针对多模态侧信道攻击的保护。Si衬底中的背面埋地金属（BBM）布线与其正面互补金属氧化物半导体（CMOS）电路统一，以实现对电磁和激光攻击的规避、检测和弹性。
Secure hardware systems are threatened by adversarial attempts on integrated circuit (IC) chips in a practical utilization environment. This article provides overviews of physical attacks on cryptographic circuits, associated vulnerabilities in an IC chip, and protection schemes in the vertical unification of systems, circuits, and packaging technologies. The design principles of on-chip monitoring circuits to sense the attackers’ attempts are discussed and tested with Si demonstrators. Physical structures are explored for secure IC chips to establish protections against multimodal side-channel attacks. The backside buried metal (BBM) wirings in a Si substrate are unified with its frontside complementary metal–oxide semiconductor (CMOS) circuits to achieve avoidance, detection, and resiliency against electromagnetic and laser attacks.