A 1–16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator
A 1–16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator
复制标题
使用宽带高线性度相位内插器进行 1–16 Gb/s 全数字时钟和数据恢复
DOI：
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发表时间：
2016
影响因子：
2.8
通讯作者：
Mark Morgan
中科院分区：
文献类型：
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作者：
Guoying Wu;D. Huang;Jingxiao Li;P. Gui;Tianwei Liu;Shita Guo;Rui Wang;Yanli Fan;S. Chakraborty;Mark Morgan
本文提出了一种基于全数字相位插值器 (PI) 的时钟和数据恢复 (CDR)，可连续适应 1 至 16 Gb/s 的任何数据速率以及 4 至 8 GHz 的正交采样时钟。提出了一种在 4-8 GHz 范围内具有高线性度的新型低功耗两步 PI (TSPI)。全数字 CDR 控制环路采用多模式相位检测方案，可支持连续数据速率。数字架构不仅消除了大型滤波电容器，而且使设计更能容忍工艺、电压和温度变化。 CDR 内核采用商用 65 nm CMOS 技术，占地 0.088 mm2，在 1.2 V 电源下以 16 Gb/s 的速度消耗 73.1 mA 的电流。 PI 的微分非线性经测量在 0.48 LSB 以内。测量结果表明，该 CDR 可以在建议的相位检测模式下工作，并且能够在高频 (4-100 MHz) 下超过同步光网络 (SONET) OC-192 抖动容限模板至少 0.2 个单位间隔，在 10 Gb/s 下具有 231 - 1 伪随机二进制序列数据模式，目标误码率为 10-12。
An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4-8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme enabling continuous data rate support. The digital architecture not only eliminates the large filtering capacitor but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm2 in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. The measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the synchronous optical networking (SONET) OC-192 jitter tolerance mask at least by 0.2 unit interval at high frequencies (4-100 MHz) with a 231 - 1 pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of 10-12.