A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems
A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems
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DOI：
10.1109/les.2011.2167213
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发表时间：
2011-09
影响因子：
1.6
通讯作者：
Qian Zhao;Y. Ichinomiya;Motoki Amagasaki;M. Iida;T. Sueyoshi
中科院分区：
文献类型：
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作者：
Qian Zhao;Y. Ichinomiya;Motoki Amagasaki;M. Iida;T. Sueyoshi
随着集成电路的尺寸已经达到纳米级，嵌入式存储器由于其低阈值电压而对单粒子翻转（SEU）或双粒子翻转（DEU）更加敏感。特别是，包含大量配置存储器来实现客户电路的可重配置系统更有可能遭受由SEU和DEU引起的软错误。在这封信中，我们开发了一个基于汉明码的错误检测和校正（EDAC）电路，可以保护配置存储器的可重构设备从SEU。评估表明，相比于传统的三重模块冗余（TMR）保护的现场可编程门阵列（FPGA）瓦片，建议的EDAC保护的FPGA瓦片显示出约2.3倍的可靠性更好的DEU的影响。此外，随着FPGA阵列大小的增加，EDAC的可靠性优势呈指数级增加。EDAC的主要缺点是它的面积开销是TMR的1.6倍。
As the size of integrated circuits has reached the nanoscale, embedded memories are more sensitive to single-event upsets (SEUs) or double-event upsets (DEUs), due to their low threshold voltage. In particular, reconfigurable systems, containing a large number of configuration memories to implement customer circuits, are more likely to suffer from soft errors caused by SEUs and DEUs. In this letter, we develop a Hamming code based error detection and correction (EDAC) circuit that can protect the configuration memory of a reconfigurable device from SEUs. Evaluation reveals that compared to the conventional triple modular redundancy (TMR) protected field-programmable gate array (FPGA) tile, the proposed EDAC protected FPGA tile shows about 2.3 times better dependability on the influence of DEUs. Moreover, as the FPGA array size increases, the dependability advantage of EDAC increases exponentially. The main drawback of EDAC is that it has about 1.6 times greater area overhead than TMR.