3D stacking induced mechanical stress effects
3D stacking induced mechanical stress effects
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3D 堆叠引起的机械应力效应
DOI：
10.1109/ectc.2014.6897304
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
E. Beyne
中科院分区：
文献类型：
--
作者：
V. Cherman;G. van der Plas;J. de Vos;A. Ivankovic;M. Lofrano;V. Simons;M. Gonzalez;K. Vanstreels;T. Wang;R. Daily;W. Guo;G. Beyer;A. la Manna;I. De Wolf;E. Beyne
本文系统地研究了三维堆叠技术对器件性能的影响。本研究采用65纳米技术，设计并制造了一种由多个应力传感器和垂直互连环路组成的特殊芯片。在芯片的不同位置检测到高达300兆帕的局部应力变化，并使用有限元建模和微拉曼光谱测量进行表征。
In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65 nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized using finite element modeling and micro-Raman spectroscopy measurements.