Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor
Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor
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DOI：
10.1109/tdmr.2012.2227261
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发表时间：
2013-03
影响因子：
2
通讯作者：
Jianjun Chen;Shuming Chen;Yibai He;Junrui Qin;Bin Liang;Biwei Liu;Pengcheng Huang
中科院分区：
文献类型：
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作者：
Jianjun Chen;Shuming Chen;Yibai He;Junrui Qin;Bin Liang;Biwei Liu;Pengcheng Huang
在本文中，提出了一种基于虚拟晶体管的新型单粒子瞬态（SET）缓解布局技术。使用90纳米双阱CMOS技术进行的技术计算机辅助设计数值模拟表明，所提出的布局技术能够有效减小SET脉冲宽度。针对反相器单元的情况对这种布局设计方法进行了深入讨论，然后将讨论扩展到其他逻辑单元。我们还将所提出的布局技术与“保护环”（用于缓解P型撞击）和“保护漏极”（用于缓解N型撞击）布局技术进行了比较，发现所提出的布局技术不仅在更大程度上缓解SET方面具有优势，而且在面积损失方面也更小。
In this paper, a novel layout technique for single-event transient (SET) mitigation based on dummy transistors is proposed. Numerical simulations using technology computer-aided design with 90-nm twin-well CMOS technology show that the proposed layout technique can efficiently reduce SET pulsewidths. This layout design methodology is thoroughly discussed for the case of the inverter cell, and the discussion is then extended to other logic cells. We also compare the proposed layout technique with the “guard ring” (for P-hit mitigation) and the “guard drain” (for N-hit mitigation) layout techniques, and we find that not only does the proposed layout technique provide the benefit of greater SET mitigation but it also presents a smaller area penalty.