Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops
Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops
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DOI：
10.1109/tvlsi.2009.2029116
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发表时间：
2011
影响因子：
2.8
通讯作者：
M. Phyu;Kangkang Fu;W. Goh;K. Yeo
中科院分区：
文献类型：
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作者：
M. Phyu;Kangkang Fu;W. Goh;K. Yeo
提出了一种新型的低功耗、高性能的显式脉冲双边沿触发灵敏放大器触发器（DET-SAFF）。通过在新的快速锁存器中引入双边沿触发机制，并采用条件预充电，DET-SAFF能够实现具有小延迟的低功耗。为了进一步降低低开关活动时的功耗，采用了时钟门控检测放大器（CG-SAFF）。广泛的布局后模拟证明，建议DET-SAFF表现出低功耗和高速性能，与现有技术的延迟和功率降低高达43.3%和33.5%，分别。当开关活动小于0.5时，建议CG-SAFF在功率降低方面表现出其优越性。在零输入开关活动期间，CG-SAFF可以实现高达86%的省电。最后，对所提出的电路进行修改，提高了共模抑制比（CMRR）DET-SAFF。
A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF.