Cryptographic Accelerators for Digital Signature Based on Ed25519
Cryptographic Accelerators for Digital Signature Based on Ed25519
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DOI：
10.1109/tvlsi.2021.3077885
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发表时间：
2021-07-01
影响因子：
2.8
通讯作者：
Mozaffari-Kermani, Mehran
中科院分区：
文献类型：
--
作者：
Bisheh-Niasar, Mojtaba;Azarderakhsh, Reza;Mozaffari-Kermani, Mehran
本文介绍了 Ed25519 数字签名算法 [Edwards 曲线数字签名算法 (EdDSA)] 的高度优化实现。与现有的数字签名算法相比，该算法在不牺牲安全性的情况下显着缩短了执行时间。尽管 EdDSA 用于许多广泛使用的协议（例如 TLS 和 SSH），但似乎很少有硬件实现仅专注于 EdDSA。因此，我们提出了两种不同的基于现场可编程门阵列 (FPGA) 的 EdDSA 实现，即适用于与 AES-128 相当的安全级别的高效高性能 Ed25519 架构。我们提出的高效 Ed25519 方案通过减少所需面积，与之前最好的工作相比，实现了 84% 以上的改进。它还具有超过 8 倍的加速性能。此外，我们提出的高性能架构显示出 21 倍的加速，每秒超过 6200 个数字签名算法，在 Xilinx Zynq-7020 FPGA 上的利用面积 x 时间方面显示出显着改进。最后，我们提出的设计中嵌入了有效的侧信道对策，这也优于以前的工作。
This article presents highly optimized implementations of the Ed25519 digital signature algorithm [Edwards curve digital signature algorithm (EdDSA)]. This algorithm significantly improves the execution time without sacrificing security, compared to exiting digital signature algorithms. Although EdDSA is employed in many widely used protocols, such as TLS and SSH, there appear to be extremely few hardware implementations that focus only on EdDSA. Hence, we propose two different field-programmable gate array (FPGA)-based EdDSA implementations, i.e., efficient and high-performance Ed25519 architectures applicable for a security level comparable to AES-128. Our proposed efficient Ed25519 scheme achieves an improvement of more than 84% compared to the best previous work by reducing the required area. It also incorporates more than 8x speedup. Furthermore, our proposed high-performance architecture shows a 21x speedup with more than 6200 digital signature algorithms per second, showing a significant improvement in terms of utilized area x time on a Xilinx Zynq-7020 FPGA. Finally, the effective side-channel countermeasures are embedded in our proposed designs, which also outperform the previous works.