Worst-Case Critical-Path Delay Analysis Considering Power-Supply Noise
Worst-Case Critical-Path Delay Analysis Considering Power-Supply Noise
复制标题
考虑电源噪声的最坏情况关键路径延迟分析
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
Harry H. Chen
中科院分区：
文献类型：
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作者：
Fang Bao;M. Tehranipoor;Harry H. Chen
随着技术的进一步扩展，在扫描测试期间对IR压降效应的不准确预测可能会导致对关键路径延迟的显著低估，并进一步导致严重的问题，例如保护带应用不足、测试逃逸、芯片误分仓等。本文提出了一种新的布局感知路径延迟测试生成方法，以最大限度地提高电源噪声对目标路径在延迟测试过程中的影响。通过计算跃迁传播概率和运行故障模拟，能够快速估计电源噪声。在此基础上，计算路径延迟故障（PDF）和过渡延迟故障（TDF）模式之间的相关性，以找到最佳序列合并模式。最终生成的路径延迟测试能够同时增加局部和全局电源噪声，从而进一步捕捉目标路径的最坏情况时序场景，实验结果表明，与标称PDF模式和最佳随机填充PDF模式相比，最终生成的PDF模式能够显著增加路径延迟。
As technology further scales, inaccurate prediction of IR-drop effect during scan testing could cause significant under estimation of the critical path delay, and further leads to serious issues such as insufficient guard band application, test escape, chip mis-binning and more. In this paper, a novel layout-aware path delay test generation method is proposed to maximize the effect of power-supply noise on target paths during delay test. It is able to estimate supply noise fast by calculating transition propagation probability and running fault simulation. Based on such estimation, the correlation between path-delay fault (PDF) and transition-delay fault (TDF) patterns is calculated to find the best sequence to merge patterns. The final generated path-delay test is able to simultaneously increase the local and global power-supply noise, thus furthur capture the worst-case timing scenarios of the target path. Experimental results show that the final PDF pattern can increase the path delay significantly comparing with the nominal PDF pattern and the best randomly-filled PDF pattern.