Ultra-low latency recurrent neural network inference on FPGAs for physics applications with hls4ml
Ultra-low latency recurrent neural network inference on FPGAs for physics applications with hls4ml
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DOI：
10.1088/2632-2153/acc0d7
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发表时间：
2022-07
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通讯作者：
E. E. Khoda-E.;D. Rankin;R. Teixeira de Lima;P. Harris;S. Hauck;Shih-Chieh Hsu;M. Kagan;V. Loncar;Chaitanya Paikara;R. Rao;S. Summers;C. Vernieri;Aaron Wang
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作者：
E. E. Khoda-E.;D. Rankin;R. Teixeira de Lima;P. Harris;S. Hauck;Shih-Chieh Hsu;M. Kagan;V. Loncar;Chaitanya Paikara;R. Rao;S. Summers;C. Vernieri;Aaron Wang
递归神经网络已被证明是高能物理中许多任务的有效架构，因此已被广泛采用。然而，由于在现场可编程门阵列（FPGA）上实现经常性架构的困难，它们在低延迟环境中的使用受到限制。在本文中，我们提出了两种类型的递归神经网络层的实现长短期记忆和门控递归单元在hls4ml框架内。我们证明，我们的实现是能够产生有效的设计，为小型和大型模型，并可以定制，以满足特定的设计要求的推理机和FPGA资源。我们展示了多个神经网络的性能和合成设计，其中许多是专门为CERN大型强子对撞机的喷气识别任务而训练的。
Recurrent neural networks have been shown to be effective architectures for many tasks in high energy physics, and thus have been widely adopted. Their use in low-latency environments has, however, been limited as a result of the difficulties of implementing recurrent architectures on field-programmable gate arrays (FPGAs). In this paper we present an implementation of two types of recurrent neural network layers—long short-term memory and gated recurrent unit—within the hls4ml framework. We demonstrate that our implementation is capable of producing effective designs for both small and large models, and can be customized to meet specific design requirements for inference latencies and FPGA resources. We show the performance and synthesized designs for multiple neural networks, many of which are trained specifically for jet identification tasks at the CERN Large Hadron Collider.