The Modeling and Synthesis of Bus Systems
The Modeling and Synthesis of Bus Systems
复制标题
总线系统的建模与综合
DOI：
10.1109/dac.1981.1585398
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发表时间：
1981
期刊：
影响因子：
--
通讯作者：
D. Siewiorek
中科院分区：
文献类型：
--
作者：
C. Tseng;D. Siewiorek
面向总线的寄存器和数据运算符互连是数字系统数据通路设计的主要模式。一项对10种处理器实现的研究表明，它们在数字设计实践中跨越了近20年，大小从微处理器到大型主机不等。从这项研究巴士风格原语和通用巴士模型的开发。通用总线模型被简化以匹配组成研究的十个处理器中的每一个。提出了一种生成总线样式设计的算法。该算法被用来生成PDP-11/40的数据路径，从而降低成本和较短的延迟比原来的实现。最后，本文讨论了总线综合算法的实现及其在CMU功能到硬件设计自动化系统中的作用。
A bus oriented interconnection of registers and data operators is the dominant mode of design for the data paths of digital systems. A study of ten processor implementations, ranging in size from microprocessors to large mainframes, spanning almost 20 years in the practice of digital design, indicated a strong similarity. From this study bus style primitives and generic bus models were developed. The generic bus models were simplified to match each of the ten processors composing the study. An algorithm for generating a bus style design is presented. The algorithm is used to generate the data paths of the PDP-11/40 resulting in lower cost and shorter delays than the original implementation. Finally, the paper concludes with a discussion of the bus synthesis algorithm's implementation and its role in the CMU functional-to-hardware Design Automation System.