FPGA-based lifting wavelet processor for real-time signal detection
FPGA-based lifting wavelet processor for real-time signal detection
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DOI：
10.1016/j.sigpro.2004.06.020
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发表时间：
2004-10
期刊：
影响因子：
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通讯作者：
K. Kuzume;K. Niijima;S. Takano
中科院分区：
文献类型：
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作者：
K. Kuzume;K. Niijima;S. Takano
本文介绍了一种用于信号检测的提升小波处理器在现场可编程门阵列（FPGA）上的实现。该处理器实现了一种算法，用于检测目标部分的信号使用整数型哈尔提升小波变换（IHLWT），我们提出的。由于我们的检测算法是非常简单的，因为在IHLWT的滤波器长度短，VLSI可以设计使用少量的电路，仅由6个乘法器和9个加法器。因此，通过构造流水线结构，可以实现目标信号的高速检测。采用硬件描述语言（HDL）设计了VLSI，并在FPGA上进行了实际仿真。通过软件生成的信号和实用采样的信号对完成的原型进行测试，其中彻底检查了涵盖多种心电图（ECG）信号的测试场景。从结果中，它被证实，所提出的处理器可以执行目标信号检测从测量的心电信号在真实的时间。
This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. Since our detection algorithm is very simple because of short filter length in the IHLWT, the VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders. Therefore, it can realize the high-speed detection of target signals by constructing a pipeline architecture. The VLSI is designed using hardware description language (HDL) and is simulated on the FPGA in practice. The completed prototype is tested through software-generated signals and utility-sampled signals, in which test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly. From the results, it is confirmed that the proposed processor can execute target signal detection from the measured ECG signals in real time.