Analysis and Design of Power, Ground and Clock Nets in High Speed Digital Integrated Circuits

本研究旨在：(a)研究GaAs和ECL电路中的电流浪涌问题，以更好地了解它们对芯片可靠性的影响；(b)开发自动化技术来分析电源、接地和时钟分配系统，以检测潜在的可靠性问题；(c)找到持久可靠性所需的设计规则；(d)将设计规则和指南纳入高性能电路设计工具。集成电路互连的传输线模型正在探索中。基于数值技术与传输线理论相结合的分析方法正在发展。为了解决有效利用芯片面积的问题，正在设计优化技术。电流浪涌的研究正在使用实验、随机和分析技术进行。

This research is to: (a) study the problem of current surges in GaAs and ECL circuits to better understand their impacts on chip reliability, (b) develop automated techniques to analyze power, ground and clock distribution systems in order to detect potential reliability problems, (c) find design rules required for enduring reliability, and (d) incorporate design rules and guidelines into tools for design of high performance circuits. Transmission line models for interconnects in IC's are being explored. Analysis methods based on numerical techniques coupled with transmission line theory are being developed. Optimization techniques are being devised for solving problems of effective utilization of chip area. The study of current surges is being approached using experimental, stochastic and analytic techniques.