Testable Approaches and Design for Array Systems

恒定可测性（或C-可测性）中的三个主题 组合电路和时序电路的同构结构是 正在调查C-可测试性方法正在扩展到 包括系统在内的新领域。 第一个主题是细胞分解 在不受限制的组件级故障模型被 分析了 把细胞分成不同的部分， 并设计一个层次化的组织， 测试过程正在调查中。第二个是C-可测试性， 使用检查和巡回方法的顺序阵列。程序 用于测试使用唯一输入输出序列的顺序阵列 正在接受检查。第三是构建的并发C可测试性， 自检（BIST）。 适合数组实现的结构 在组合和顺序细胞中， 延迟时间和硬件开销。

Three topics in constant testability (or C-testability) for homogeneous structures of combinational and sequential circuits is being investigated. C-testability methods are being extended into new areas including systems. The first topic is cell decomposition where an unrestricted, component level fault model is being analyzed. Questions of dividing a cell into components that can be tested, and of devising a hierarchal organization for the testing process are being investigated. Second is C-testability of sequential arrays using checking and touring methods. Procedures for testing sequential arrays using unique input-output sequences are being examined. Third is concurrent C-testability for Built- in-Self-Test (BIST). Structures amenable to array implementation in combinational and sequential cells are being explored to assess latency time and hardware overhead.