Testable Approaches and Design for Array Systems

关于组合电路和时序电路的同质结构的常量可测性(或C-可测性)的三个主题正在被研究。C-可测试性方法正在扩展到包括系统在内的新领域。第一个主题是单元分解，其中分析了一个不受限制的组件级故障模型。正在研究将细胞分成可测试的组件，以及为测试过程设计层级组织的问题。第二个问题是序列数组的C-可测性。正在审查使用独特的输入-输出序列测试顺序阵列的程序。第三，内建自测试(BIST)的并发C测试性。正在探索能够在组合和顺序单元中实现阵列的结构，以评估等待时间和硬件开销。

Three topics in constant testability (or C-testability) for homogeneous structures of combinational and sequential circuits is being investigated. C-testability methods are being extended into new areas including systems. The first topic is cell decomposition where an unrestricted, component level fault model is being analyzed. Questions of dividing a cell into components that can be tested, and of devising a hierarchal organization for the testing process are being investigated. Second is C-testability of sequential arrays using checking and touring methods. Procedures for testing sequential arrays using unique input-output sequences are being examined. Third is concurrent C-testability for Built- in-Self-Test (BIST). Structures amenable to array implementation in combinational and sequential cells are being explored to assess latency time and hardware overhead.