Testable Approaches and Design for Array Systems

本文研究了组合电路和顺序电路齐次结构的恒定可测性（或c -可测性）的三个主题。可测试性方法正在扩展到新的领域，包括系统。第一个主题是单元分解，其中分析一个不受限制的组件级故障模型。将细胞划分为可测试的组件，以及为测试过程设计层次结构的问题正在研究中。其次是使用检查和遍历方法的顺序数组的c可测试性。正在审查使用唯一输入-输出序列测试顺序阵列的程序。第三是内置自检（BIST）的并发c可测性。在组合和顺序单元中适合数组实现的结构正在被探索，以评估延迟时间和硬件开销。

Three topics in constant testability (or C-testability) for homogeneous structures of combinational and sequential circuits is being investigated. C-testability methods are being extended into new areas including systems. The first topic is cell decomposition where an unrestricted, component level fault model is being analyzed. Questions of dividing a cell into components that can be tested, and of devising a hierarchal organization for the testing process are being investigated. Second is C-testability of sequential arrays using checking and touring methods. Procedures for testing sequential arrays using unique input-output sequences are being examined. Third is concurrent C-testability for Built- in-Self-Test (BIST). Structures amenable to array implementation in combinational and sequential cells are being explored to assess latency time and hardware overhead.