RIA: A Theoretical Framework for Programming and Design Bit-Level Processor Arrays

RIA：位级处理器阵列编程和设计的理论框架

• 批准号: 9110940
• 负责人: Weijia Shang
• 金额: $ 5.92万
• 依托单位: University of Louisiana at Lafayette
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1991
• 资助国家: 美国
• 起止时间: 1991-07-01 至 1994-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9110940&HistoricalAwards=false
• 关键词: RIA; Theoretical; Framework; Programming; Design

The objective of this research is the development of a theoretical framework based on which a software tool can be developed to program and design systematically bit-level processor arrays. The resulting software tool should be portable and explore fully the parallelism at bit-level and word-level which current system software of bit level systems lacks or does not fully explore. It can reduce significantly the programming burdens on users and improve the situation that only a low percentage of the performance offered by hardware is utilized because of the insufficient support of system software. The class of algorithms for which the theoretical framework is developed are frequently used in digital signal processing, image processing and other scientific computations. This project is divided into three steps: (1) expanding the conventional algorithm at word-level into bit-level to explore the parallelism at bit-level; (2) analyzing the parallelism and dependence structure of these n-dimensional (often four or five dimensional) bit-level algorithms (algorithms with n nested loops); (3) finding time-optimal mapping into (k-l) dimensional (often two dimensional) bit-level processor arrays without computational conflicts based on the dependence structure.

本研究的目的是发展一种理论 一个软件工具可以开发的框架， 系统地编程和设计位级处理器阵列。 的 由此产生的软件工具应该是便携式的，并充分探索 位级和字级的并行性， 比特级系统的软件缺乏或没有充分探索。 它 可以显著减少用户的编程负担， 改善只有低百分比的性能的情况 由于支持不足， 系统软件。 类的算法， 理论框架的发展是经常使用的数字 信号处理、图像处理和其他科学 计算。 本项目分为三个步骤：（1） 将传统的字级算法扩展到位级 探讨位级并行性;（2）分析 这些n维的并行性和依赖性结构（通常 四维或五维）位级算法（n （3）找到到（k-l）的时间最优映射 一维（通常是二维）位级处理器阵列 而没有基于依赖结构的计算冲突。