RIA: A Theoretical Framework for Programming and Design Bit-Level Processor Arrays

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The objective of this research is the development of a theoretical framework based on which a software tool can be developed to program and design systematically bit-level processor arrays. The resulting software tool should be portable and explore fully the parallelism at bit-level and word-level which current system software of bit level systems lacks or does not fully explore. It can reduce significantly the programming burdens on users and improve the situation that only a low percentage of the performance offered by hardware is utilized because of the insufficient support of system software. The class of algorithms for which the theoretical framework is developed are frequently used in digital signal processing, image processing and other scientific computations. This project is divided into three steps: (1) expanding the conventional algorithm at word-level into bit-level to explore the parallelism at bit-level; (2) analyzing the parallelism and dependence structure of these n-dimensional (often four or five dimensional) bit-level algorithms (algorithms with n nested loops); (3) finding time-optimal mapping into (k-l) dimensional (often two dimensional) bit-level processor arrays without computational conflicts based on the dependence structure.