RIA: A Theoretical Framework for Programming and Design Bit-Level Processor Arrays

这项研究的目的是开发一个理论框架，在此基础上可以开发一个软件工具来系统地对位级处理器阵列进行编程和设计。由此产生的软件工具应该是可移植的，并且充分探索了当前位级系统的系统软件缺乏或没有充分探索的位级和字级的并行性。它可以大大减轻用户的编程负担，改善由于系统软件支持不足而只利用硬件提供的低百分比性能的情况。为其开发理论框架的这类算法经常用于数字信号处理、图像处理和其他科学计算。该项目分为三个步骤：(1)将传统的字级算法扩展到位级，以探索位级的并行性：(2)分析这些n维(通常是四维或五维)位级算法(具有n个嵌套循环的算法)的并行性和依赖结构；(3)基于依赖结构，寻找到(k-L)维(通常是二维)比特级处理器阵列的无计算冲突的时间最优映射。

The objective of this research is the development of a theoretical framework based on which a software tool can be developed to program and design systematically bit-level processor arrays. The resulting software tool should be portable and explore fully the parallelism at bit-level and word-level which current system software of bit level systems lacks or does not fully explore. It can reduce significantly the programming burdens on users and improve the situation that only a low percentage of the performance offered by hardware is utilized because of the insufficient support of system software. The class of algorithms for which the theoretical framework is developed are frequently used in digital signal processing, image processing and other scientific computations. This project is divided into three steps: (1) expanding the conventional algorithm at word-level into bit-level to explore the parallelism at bit-level; (2) analyzing the parallelism and dependence structure of these n-dimensional (often four or five dimensional) bit-level algorithms (algorithms with n nested loops); (3) finding time-optimal mapping into (k-l) dimensional (often two dimensional) bit-level processor arrays without computational conflicts based on the dependence structure.