RIA -- MTV: A Multiple Event Timing Verifier

这项研究是关于电路时序特性的验证。该方法是开发一个多事件时序验证器，它工作在门级，表示信号的多个跃迁，并工作在同步和异步电路上。正在探索在低阶多项式时间内执行分析并使用准确捕捉系统数字行为的数据表示的算法。正在开发的算法设计和相关软件包括以下功能：验证具有非平凡输入时序的电路，允许对信号进行多次转换，进行功能分析以消除错误路径，允许设计人员轻松输入和检查数据，验证不同的时钟规则，以及检测各种时序问题，如时钟频率未满足、脉冲缩短、危险和竞争。

This research is on verification of circuit timing properties. The approach is to develop a multiple event timing verifier, which operates at gate level, represents multiple transitions on signals, and works on synchronous as well as asynchronous circuits. Algorithms that perform analysis in low order polynomial time and use a data representation that accurately captures the digital behavior of the system are being explored. Algorithm designs and related software being developed include functions such as: verifying circuits with non-trivial input timing, allowing multiple transitions on signals, doing functional analysis to eliminate false paths, allowing designers to input and examine data easily, verifying different clocking disciplines, and detecting various timing problems, such as clock rate not met, pulse shortening, hazards and races.