NSF Young Investigator Award: A Design Language for Asynchronous Circuit Synthesis

NSF 青年研究员奖：异步电路综合设计语言

• 批准号: 9257987
• 负责人: Steven Burns
• 金额: $ 27.5万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1992
• 资助国家: 美国
• 起止时间: 1992-09-15 至 1998-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9257987&HistoricalAwards=false
• 关键词: NSF; Young; Investigator; Award; Design

Burns This research is on developing a unifying design language and framework in which asynchronous circuit designs can be completely specified, and in which decisions made during synthesis of the implementation can be recorded. The language is an extension of Hoare's CSP with a means to specify structural hierarchy with a refinement hierarchy superimposed upon it. The research consists of three interconnected tasks: language definition; developing tools such as a parser, flattener, view generator, handshaking expansions, and production rule sets; and application of the tools to a large design or a real time system. An algorithm for determining the maximum time separation of event occurrences in a concurrent system is being developed.

本研究旨在开发一种统一的设计语言和框架，其中异步电路设计可以完全指定，并且可以记录在综合实现过程中做出的决策。该语言是Hoare的CSP的扩展，通过在其上添加细化层次来指定结构层次。研究包括三个相互关联的任务：语言定义；开发诸如解析器、平坦器、视图生成器、握手扩展和生产规则集等工具；并将这些工具应用到大型设计或实时系统中。目前正在开发一种算法，用于确定并发系统中事件发生的最大时间间隔。