Research Initiation Award: Communication and Fault Tolerance in Parallel Computers

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The project focuses on two important inter-related issues in the design of large scale parallel computers: inter-processor communication and fault-tolerance. The nature of the research is one of synthesizing theoretical and practical approaches to parallel computing. Efficient inter-processor communication is at the heart of efficient parallel computing. With some exceptions, much of the theoretical work has focused on provably optimal algorithms that are often too complex to implement. On the other hand, much of the implemented routing hardware have simpler designs but lack theoretical guarantees as to their performance. This project will attempt to bridge this gap and focus on simple routing schemes that are provably good (though not always optimal). Fault tolerance is becoming ever-increasingly important in the world of parallel computers with a large number of fallible components. The study of fault-tolerant routing schemes focuses on algorithms that can route packets efficiently even in the presence of faulty switches. The two research directions represent very important but largely uncharted territory. The first concerns the question of intrinsic limitations on the fault tolerance of networks. The second research direction concerns reconfiguring in increasingly important class of parallel computers known as heterogeneous parallel computers.