Grid Optimization and Adaptation in Semiconductor Process and Device Problems

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9412475 Carey Grid refinement-solution is a key problem area and critical "bottleneck" to semiconductor device and process simulation (e.g. see the Semiconductor Industry Association Roadmap, 1993). The open issues range from he basic questions of efficient generation of unstructured adaptive 2D and 3D grids, to reliable error indicators and enhanced solution techniques that exploit the grid. The present research builds on the investigators' previous experience in adaptive grids to focus on the grid problem for semiconductor technology CAD. There are five main thrusts to the grid research for semiconductor problems: 1. Two and three-dimensional unstructured and moving grids for semiconductor device and process applications: 2. Quadtree/octree data structures and adaptive refinement/redistribution; 3. A posteriori error analyses and error indicators for refinement and reliability calculation in the device and process problems; 4. Refinement-Solution strategies to exploit the evolving grid and enhance computational efficiency; 5. Benchmark studies and application to representative device and process problems.