Engineering Faculty Internship: A Seamless Environment for Productivity Enhancement; Design Synthesis

点击翻译按钮获取中文摘要

9412705 Pandya This summer faculty internship permits the investigators to be involved in industrial designs, evolve their own realistic design examples, incorporate such experiences in the Very Large Scale Integrated Circuits (VLSI) courses taught at the university and develop video tutorials useful for both the students and industry engineers. This project addresses the intermediate-level tasks and uses two separate commercial tools for mapping from top-level design, synthesis with pre-designed/vendor-supplied/custom-built modules, optimization and back-annotation interfaces to low-level or physical design. This project's material is targeted to senior undergraduate/graduate courses on VLSI System design.