SBIR Phase I: Scalable Distributed Parallel Logic Simulation for Large Deep Submicron VLSI Designs

这个小型企业创新研究第一阶段项目将研究使用先进的Unix工作站对大型深亚微米VLSI设计进行并行逻辑模拟的可行性。集成电路上实现的晶体管数量每2到3年翻一番。这一事实影响到设计方法的所有方面，包括需要几天到几周的计算来验证VLSI设计的正确性的设计仿真。此外，包含数百万门的设计不能被模拟为单个系统，因为它们要么太大，不适合今天的工作站，要么产生太多的页面错误，使得模拟太慢。该项目将研究一种可扩展的体系结构，用于在Unix工作站上执行分布式和并行数字逻辑模拟。分布式功能处理大小并消除页面错误问题。可扩展和并行的功能使模拟数百万门设计成为可能。第一阶段的工作将建立体系结构需求，开发体系结构，在系统级别派生必要的算法，开发规模版本，并分析可以获得的潜在性能。这项工作将使用最先进的逻辑模拟和并行处理技术。将验证该架构是否符合电子设计自动化(EDA)行业标准，以便实现商业化。该体系结构具有开发和商业化三种产品的潜力：(1)可扩展分布式并行Verilog(仿真器)；(2)可扩展分布式并行VHDL仿真器；(3)可扩展分布式并行协同仿真器。

This Small Business Innovation Research Phase I project will study the feasibility of parallel logic simulation for large deep submicron VLSI designs using advanced UNIX workstations. The number of transistors implemented on an integrated circuit doubles every 2 to 3 years. This fact affects all the aspects of the design methodology, including design simulation that takes several days to weeks of computing to verify the correctness of a VLSI design. Moreover, designs that contain multi-million gates can not be simulated as a single system since they are either too big to fit on today's workstations, or generate too many page faults making the simulation too slow. This project will investigate a scalable architecture for performing distributed and parallel digital logic simulation on UNIX workstations. The distributed feature deals with the size and eliminates the page-fault problem. The scalable and parallel feature makes it possible to simulate multi-million gate designs. The Phase I effort will establish architecture requirements, develop the architecture, derive necessary algorithms at the system level, develop a scaled version and analyze the potential performance that can be obtained. State-of-the-art logic simulation and parallel processing technology will be used for this effort. Verification will be made that the architecture is compliant with the Electronic Design Automation (EDA) industry standard so that commercialization is possible. The proposed architecture has the potential to develop and commercialize three products: (1) Scalable Distributed Parallel Verilog( Simulator; (2) Scalable Distributed Parallel VHDL Simulator; and, (3) Scalable Distributed Parallel Co-Simulator.