SBIR Phase I: Scalable Distributed Parallel Logic Simulation for Large Deep Submicron VLSI Designs

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This Small Business Innovation Research Phase I project will study the feasibility of parallel logic simulation for large deep submicron VLSI designs using advanced UNIX workstations. The number of transistors implemented on an integrated circuit doubles every 2 to 3 years. This fact affects all the aspects of the design methodology, including design simulation that takes several days to weeks of computing to verify the correctness of a VLSI design. Moreover, designs that contain multi-million gates can not be simulated as a single system since they are either too big to fit on today's workstations, or generate too many page faults making the simulation too slow. This project will investigate a scalable architecture for performing distributed and parallel digital logic simulation on UNIX workstations. The distributed feature deals with the size and eliminates the page-fault problem. The scalable and parallel feature makes it possible to simulate multi-million gate designs. The Phase I effort will establish architecture requirements, develop the architecture, derive necessary algorithms at the system level, develop a scaled version and analyze the potential performance that can be obtained. State-of-the-art logic simulation and parallel processing technology will be used for this effort. Verification will be made that the architecture is compliant with the Electronic Design Automation (EDA) industry standard so that commercialization is possible. The proposed architecture has the potential to develop and commercialize three products: (1) Scalable Distributed Parallel Verilog( Simulator; (2) Scalable Distributed Parallel VHDL Simulator; and, (3) Scalable Distributed Parallel Co-Simulator.