CAREER: QoS Architecture for General Purpose Network Computing.

9876117CAREER：指令带宽优化Wilson C.这个项目重新审视了编译器优化如何影响商业应用程序中的一个瓶颈：获取指令的成本。 标准的编译器优化用带宽换取更快的指令序列，这对于具有良好指令局部性的应用程序效果很好。 不幸的是，最近的研究表明，指令带宽是一个性能限制因素，在许多商业应用，如数据库，电路模拟器和多媒体程序。 此外，处理器体系结构的技术趋势也将增加应用程序对指令带宽的需求。 拟议的研究将探讨这些问题的几种解决方案。 首先，两个新的编译器优化，以提高利用率的指令缓存，指令缓存调度和代码分解，将被调查。 对商业应用的跟踪分析将用于量化其效益。 第二，传统的编译器优化将被重新检查和重新设计，目标是使它们对指令缓存的利用率敏感。最后，将探索架构变化，以支持编译器和处理器之间的显式合作，从而更有效地利用指令缓存。 这项研究将提供一个更好的理解编译器应该如何优化大型的商业应用程序，这是一个领域，仍然相对未审查的研究社区。

9876117CAREER: Compiler Optimizations for Instruction BandwidthWilson C. HsiehThis project reexamines how compiler optimization affects one of thebottlenecks in commercial applications: the cost of fetchinginstructions. Standard compiler optimizations trade instructionbandwidth for faster instruction sequences, which works well forapplications that have good instruction locality. Unfortunately,recent studies have shown that instruction bandwidth is aperformance-limiting factor in many commercial applications, such asdatabases, circuit simulators, and multimedia programs. In addition,technology trends in processor architectures will also increaseapplications' demands for instruction bandwidth. The proposedresearch will explore several solutions to these problems. First, twonew compiler optimizations to improve utilization of the instructioncache, instruction cache scheduling and code factoring, will beinvestigated. Trace analysis of commercial applications will be usedto quantify their benefits. Second, traditional compileroptimizations will be reexamined and redesigned as necessary, with thegoal of making them sensitive to instruction cache utilization.Finally, architectural changes to support explicit cooperation betweenthe compiler and processor to make more efficient use of theinstruction cache will be explored. This research will provide abetter understanding of how compilers should optimize large,commercial applications, which is a field that has remained relativelyunexamined in the research community.