CAREER: QoS Architecture for General Purpose Network Computing.

9876117 CAREER：指令带宽的编译器优化Wilson C.Hsih这个项目重新研究了编译器优化如何影响商业应用程序中的瓶颈之一：获取指令的成本。标准编译器优化以指令带宽为代价换取更快的指令序列，这对具有良好指令局部性的应用程序很有效。遗憾的是，最近的研究表明，在许多商业应用中，指令带宽是性能限制因素，例如数据库、电路模拟器和多媒体程序。此外，处理器体系结构的技术趋势也将增加应用程序对指令带宽的需求。提出的研究将探索这些问题的几个解决方案。首先，将研究两个新的编译器优化，以提高指令高速缓存的利用率，指令高速缓存调度和代码分解。将使用对商业应用的跟踪分析来量化它们的好处。其次，传统的编译器优化将根据需要进行重新检查和重新设计，目标是使它们对指令高速缓存的使用敏感。最后，将探索支持编译器和处理器之间显式合作的体系结构变化，以更有效地利用指令高速缓存。这项研究将更好地理解编译器应该如何优化大型商业应用程序，这是一个在研究界仍然相对未被研究的领域。

9876117CAREER: Compiler Optimizations for Instruction BandwidthWilson C. HsiehThis project reexamines how compiler optimization affects one of thebottlenecks in commercial applications: the cost of fetchinginstructions. Standard compiler optimizations trade instructionbandwidth for faster instruction sequences, which works well forapplications that have good instruction locality. Unfortunately,recent studies have shown that instruction bandwidth is aperformance-limiting factor in many commercial applications, such asdatabases, circuit simulators, and multimedia programs. In addition,technology trends in processor architectures will also increaseapplications' demands for instruction bandwidth. The proposedresearch will explore several solutions to these problems. First, twonew compiler optimizations to improve utilization of the instructioncache, instruction cache scheduling and code factoring, will beinvestigated. Trace analysis of commercial applications will be usedto quantify their benefits. Second, traditional compileroptimizations will be reexamined and redesigned as necessary, with thegoal of making them sensitive to instruction cache utilization.Finally, architectural changes to support explicit cooperation betweenthe compiler and processor to make more efficient use of theinstruction cache will be explored. This research will provide abetter understanding of how compilers should optimize large,commercial applications, which is a field that has remained relativelyunexamined in the research community.