A Terabit IP Router with Advanced QoS Support

互联网被广泛认为是下一代信息基础设施最容易到达的平台。虽然IP/DWDM(密集波分复用互联网协议)技术已经被证明可以在单根光纤上传输1太比特/S带宽，但以1太比特/S的速度路由IP分组的能力仍有待观察。此外，为了为下一代互联网(NGI)提供不同的服务质量(Qos)要求，IETF建议采用资源预留信令协议(RSVP)的互联网综合业务(IIS)。虽然已经提出了几种算法来保证保证业务流的严格延迟界限，但如何在太比特/S的聚合速率下实现这些算法仍然是一个挑战。该方案通过设计一个T比特IP路由器的大容量交换结构并严格控制路由器输入和输出端口的分组延迟来解决这一问题。建议的T比特IpSwitch路由器由多个路由模块(RM)组成，这些模块通过快速交换结构互连。每个RM独立地转发到达的分组，从而允许路由器灵活地扩展到太比特/S。通过应用以下创新，可以在太比特/S实现对IIS的支持。首先，提出了一种新的双轮询(DRR)仲裁方案，以提供在具有中等加速比的无阻塞输入输出缓冲交叉开关分组交换机的输入端口上的统计有界延迟。DRR是一种分布式交换控制方案，其中输入选择和输出竞争解决由两组独立的轮询仲裁器分开处理。第二，提出了一种新的令牌隧道机制来实现T比特/S速率的DRR方案。结果表明，采用最先进的0.25微米CMOS工艺，一台256×256 TB/S分组交换机的仲裁时间可以缩短到10 ns。该方案还可以扩展以处理多优先级业务。为了验证这一概念的可行性，将设计一个实现DRR方案的专用集成电路(ASIC)。最后，分组公平队列(PFQ)被证明能够为IIS提供延迟界限保证。它将用于路由器的输出端口。到达的数据包通常会根据其承诺的速率加上时间戳。然而，时间戳的计算和排序一直是高速网络面临的巨大挑战，尤其是需要支持数十万流的网络。为此，提出了一种新的基于随机存储器的搜索引擎，利用现成的部件低成本地实现每个输出端口10 Gb/S的PFQ调度器，同时支持数十万流量；此外，由于Internet网络环境的异构性，需要分层的分组调度来适应不同的服务类别和多个互联网服务提供商(ISP)。整形器-调度器方案已经被证明能够在分层分组调度环境中提供紧延迟界限。遗憾的是，该方案非常复杂，并且没有被证明在高速和低成本下是可行的，特别是对于分组媒体。为此，提出了一种既适用于ATM网络又适用于分组网络的通用整形调度器。RSE的概念将被扩展到实现通用整形调度器的二维RSE(2-D RSE)。为了证明这一概念的可行性，还将制作一个2-D RSE原型。所有原型和开发的技术都将可移植到业界，以加快太比特IP路由器在NGI中的部署。

The Internet is widely considered as the most reachable platform of next-generation information infrastructure. Although IP/DWDM (internet protocol over dense wavelength division multiplexing) technology has been demonstrated to transport 1 terabit/s bandwidth over a single fiber, the capability of routing IP packets at 1 terabit/s still remains to be seen. Furthermore, in order to provide differentquality-of-service (QoS) requirements for the Next Generation Internet (NGI), IETF has suggested the Internet Integrated Services (IIS) with resource ReSerVation signaling protocol (RSVP). Although severalalgorithms have been proposed to guarantee the stringent delay bound for the guarantee service flows, how to implement them at the aggregate rate of terabit/s remains challenging.This proposal tackles the problem by designing a large-capacity switch fabric for a terabit IP router and tightly controlling packet delay at the input and output ports of the router. The proposed terabit IPswitch router consists of multiple routing modules (RMs) that are interconnected by a fast switch fabric. Each RM forwards arriving packets independently, thus allowing the router to scale flexibly up to terabit/s. With the application of the following innovations, supporting the IIS at terabit/s is conceivably achievable.First, a novel dual round robin (DRR) arbitration scheme is proposed to provide statistically bounded delay at the input ports of a nonblocking input-output buffered crossbar packet switch with a moderate speedup. The DRR is a distributed switch control scheme, in which input selection and output contention resolution are separatedly handled by two independent sets of round-robin arbiters. The switch is used to provide high speed interconnection among RM's. By using bit-slice technique with multiple switch planes, the switch operation speed is reduced and can be implemented with low-cost CMOS technology.Second, a novel token tunneling mechanism is proposed to implement the DRR scheme at terabit/s. It is shown that with state-of-the-art 0.25-micron CMOS technology, the arbitration time can be as small as10 ns for a 256x256 Tb/s packet switch. This scheme can also be extended to handle multiple-priority traffic. To demonstrate the feasibility of the concept, an application specific integrated circuit (ASIC) that implements the DRR scheme will be prototyped.Finally, packet fair queuing (PFQ) has been proven capable of providing delay bound guarantee for the IIS. It will be used at the output ports of the router. Arrival packets are usually time stamped based on their committed rates. However, time stamp's computation and sorting always pose a great challenge for high speed networks, especially with hundreds of thousands of flows that need to be supported. Therefore, a novel RAM-based searching engine (RSE) is proposed to implement the PFQ scheduler at 10 Gb/s for each outputport at low cost by using off-shelf parts while supporting hundreds of thousands of flows.Furthermore, due to the heterogeneous networking environment in the Internet, hierarchical packet scheduling is required to accommodate different service classes and multiple Internet Service Providers(ISP's). The shaper-scheduler scheme has been proven capable of providing tight delay bound in the hierarchical packet scheduling environment. Unfortunately, the scheme is very complicated and has notbeen shown feasible at high speed and at low cost, especially for packet media. Therefore, a general shaper-scheduler is proposed for both ATM and packet networks. The concept of the RSE will be extendedto a two-dimensional RSE (2-D RSE) that implements the general shaper-scheduler. To demonstrate the feasibility of the concept, a 2-D RSE will also be prototyped.All the prototypes and the developed technologies will be made transferable to the industry in order to expedite the deployment of the terabit IP routers in the NGI.