A Terabit IP Router with Advanced QoS Support
具有高级 QoS 支持的太比特 IP 路由器
基本信息
- 批准号:9906673
- 负责人:
- 金额:$ 45.42万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:1999
- 资助国家:美国
- 起止时间:1999-10-01 至 2003-09-30
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
The Internet is widely considered as the most reachable platform of next-generation information infrastructure. Although IP/DWDM (internet protocol over dense wavelength division multiplexing) technology has been demonstrated to transport 1 terabit/s bandwidth over a single fiber, the capability of routing IP packets at 1 terabit/s still remains to be seen. Furthermore, in order to provide differentquality-of-service (QoS) requirements for the Next Generation Internet (NGI), IETF has suggested the Internet Integrated Services (IIS) with resource ReSerVation signaling protocol (RSVP). Although severalalgorithms have been proposed to guarantee the stringent delay bound for the guarantee service flows, how to implement them at the aggregate rate of terabit/s remains challenging.This proposal tackles the problem by designing a large-capacity switch fabric for a terabit IP router and tightly controlling packet delay at the input and output ports of the router. The proposed terabit IPswitch router consists of multiple routing modules (RMs) that are interconnected by a fast switch fabric. Each RM forwards arriving packets independently, thus allowing the router to scale flexibly up to terabit/s. With the application of the following innovations, supporting the IIS at terabit/s is conceivably achievable.First, a novel dual round robin (DRR) arbitration scheme is proposed to provide statistically bounded delay at the input ports of a nonblocking input-output buffered crossbar packet switch with a moderate speedup. The DRR is a distributed switch control scheme, in which input selection and output contention resolution are separatedly handled by two independent sets of round-robin arbiters. The switch is used to provide high speed interconnection among RM's. By using bit-slice technique with multiple switch planes, the switch operation speed is reduced and can be implemented with low-cost CMOS technology.Second, a novel token tunneling mechanism is proposed to implement the DRR scheme at terabit/s. It is shown that with state-of-the-art 0.25-micron CMOS technology, the arbitration time can be as small as10 ns for a 256x256 Tb/s packet switch. This scheme can also be extended to handle multiple-priority traffic. To demonstrate the feasibility of the concept, an application specific integrated circuit (ASIC) that implements the DRR scheme will be prototyped.Finally, packet fair queuing (PFQ) has been proven capable of providing delay bound guarantee for the IIS. It will be used at the output ports of the router. Arrival packets are usually time stamped based on their committed rates. However, time stamp's computation and sorting always pose a great challenge for high speed networks, especially with hundreds of thousands of flows that need to be supported. Therefore, a novel RAM-based searching engine (RSE) is proposed to implement the PFQ scheduler at 10 Gb/s for each outputport at low cost by using off-shelf parts while supporting hundreds of thousands of flows.Furthermore, due to the heterogeneous networking environment in the Internet, hierarchical packet scheduling is required to accommodate different service classes and multiple Internet Service Providers(ISP's). The shaper-scheduler scheme has been proven capable of providing tight delay bound in the hierarchical packet scheduling environment. Unfortunately, the scheme is very complicated and has notbeen shown feasible at high speed and at low cost, especially for packet media. Therefore, a general shaper-scheduler is proposed for both ATM and packet networks. The concept of the RSE will be extendedto a two-dimensional RSE (2-D RSE) that implements the general shaper-scheduler. To demonstrate the feasibility of the concept, a 2-D RSE will also be prototyped.All the prototypes and the developed technologies will be made transferable to the industry in order to expedite the deployment of the terabit IP routers in the NGI.
互联网被广泛认为是下一代信息基础设施中可达性最高的平台。虽然IP/DWDM(密集波分复用的互联网协议)技术已被证明可以在单根光纤上传输1tb /s的带宽,但以1tb /s的速度路由IP数据包的能力仍有待观察。此外,为了向下一代互联网(NGI)提供不同的服务质量(QoS)要求,IETF建议使用带有资源预留信令协议(RSVP)的互联网集成服务(IIS)。虽然已经提出了几种算法来保证保证服务流的严格延迟界限,但如何在太比特/秒的总速率下实现它们仍然是一个挑战。本文通过设计一种大容量的太比特IP路由器交换结构,并严格控制路由器输入和输出端口的数据包延迟来解决这个问题。提出的太比特IPswitch路由器由多个路由模块(rm)组成,这些路由模块通过快速交换结构相互连接。每个RM独立转发到达的数据包,从而允许路由器灵活扩展到tb /s。通过以下创新的应用,支持太比特/秒的IIS是可以实现的。首先,提出了一种新的双轮询(DRR)仲裁方案,在非阻塞输入输出缓冲交叉分组交换机的输入端口提供统计上有界的延迟,并具有适度的加速。DRR是一种分布式开关控制方案,其中输入选择和输出争用解决分别由两组独立的轮循仲裁器处理。交换机用于提供RM之间的高速互连。将位片技术应用于多开关平面,降低了开关操作速度,并可采用低成本的CMOS技术实现。其次,提出了一种新的令牌隧道机制来实现兆位/秒的DRR方案。研究表明,采用最先进的0.25微米CMOS技术,对于256x256tb /s的分组交换机,仲裁时间可以小到10 ns。该方案还可以扩展到处理多优先级流量。为了证明该概念的可行性,将对实现DRR方案的专用集成电路(ASIC)进行原型设计。最后,证明了包公平排队(PFQ)能够为IIS提供延迟绑定保证。它将用于路由器的输出端口。到达数据包通常根据其承诺的速率打上时间戳。然而,对于高速网络来说,时间戳的计算和排序一直是一个巨大的挑战,特别是需要支持数十万个流的情况下。为此,提出了一种新的基于ram的搜索引擎(RSE),通过使用现成的部件,在支持数十万流的同时,以低成本实现每个输出端口10gb /s的PFQ调度器。此外,由于Internet的异构网络环境,需要分层分组调度来适应不同的业务类别和多个Internet服务提供商(ISP)。在分层分组调度环境下,形状调度器方案具有较强的延迟约束。不幸的是,该方案非常复杂,并且在高速和低成本的情况下,特别是对于分组媒体,还没有被证明是可行的。因此,本文提出了一种适用于ATM和分组网络的通用形状调度器。RSE的概念将扩展到二维RSE (2-D RSE),实现通用的成形调度程序。为了证明这一概念的可行性,还将制作一个2d RSE原型。所有的原型和开发的技术将被转移到工业界,以加快在NGI部署太比特IP路由器。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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H. Jonathan Chao其他文献
A Per-Flow Based Node Architecture for Integrated Services Packet Networks
- DOI:
10.1023/a:1016608221139 - 发表时间:
2001-01-01 - 期刊:
- 影响因子:2.300
- 作者:
Dapeng Wu;Yiwei Thomas Hou;Bo Li;H. Jonathan Chao - 通讯作者:
H. Jonathan Chao
Design of an ATM switch for handoff support
- DOI:
10.1023/a:1019239225687 - 发表时间:
2000-01-01 - 期刊:
- 影响因子:2.100
- 作者:
Heechang Kim;H. Jonathan Chao - 通讯作者:
H. Jonathan Chao
The importance of switch dimension for energy-efficient datacenter design
- DOI:
10.1016/j.comcom.2014.02.017 - 发表时间:
2014-09-01 - 期刊:
- 影响因子:
- 作者:
Indra Widjaja;Anwar Walid;Yanbin Luo;Yang Xu;H. Jonathan Chao - 通讯作者:
H. Jonathan Chao
Cutting the Electricity Cost of Distributed Datacenters Through Smart Workload Dispatching
通过智能工作负载调度降低分布式数据中心的电力成本
- DOI:
- 发表时间:
2013 - 期刊:
- 影响因子:0
- 作者:
Zehua Guo;Z. Duan;Yang Xu;H. Jonathan Chao - 通讯作者:
H. Jonathan Chao
In-network Congestion-aware Load Balancing at Transport Layer
传输层的网络内拥塞感知负载平衡
- DOI:
10.1109/nfv-sdn47374.2019.9040109 - 发表时间:
2018 - 期刊:
- 影响因子:0
- 作者:
Ashkan Aghdai;Michael I.;Yang Xu;Charles H.;H. Jonathan Chao - 通讯作者:
H. Jonathan Chao
H. Jonathan Chao的其他文献
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{{ truncateString('H. Jonathan Chao', 18)}}的其他基金
MRI: Acquisition of a Data Center Testbed for Security and Resilience Research
MRI:获取用于安全性和弹性研究的数据中心测试台
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1229218 - 财政年份:2012
- 资助金额:
$ 45.42万 - 项目类别:
Standard Grant
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MRI:采购网络安全处理器设计研究设备
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0619741 - 财政年份:2006
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$ 45.42万 - 项目类别:
Standard Grant
A Quasi-Static Optoelectronic ATM Switch
准静态光电ATM开关
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9814856 - 财政年份:1999
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$ 45.42万 - 项目类别:
Standard Grant
Acquisition of Equipment for High-Speed Networking (ATM) Research
采购高速网络(ATM)研究设备
- 批准号:
9413803 - 财政年份:1994
- 资助金额:
$ 45.42万 - 项目类别:
Standard Grant
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