CAREER: Architecture Issues in DRAM Devices and Systems

处理器和存储器速度之间的差距是当今计算机系统中的主要瓶颈。增加DRAM带宽和减少访问时间是解决内存延迟问题的关键。有一个相对缺乏的DRAM设备和系统的架构研究，因此，有许多基本的问题，代表在该领域的开放研究。本项目研究DRAM系统设计中各种技术的效果。例子包括支持并发访问和确定现代CPU可以利用这种支持的程度;多个通道的影响，以及它们是否应该联合在一起以增加带宽或独立运行;以及银行的影响及其对DSP和嵌入式应用的最佳程度。 对于突发模式的DRAM，最佳的突发大小，以适应并发性和快速的端到端延迟在这个项目中进行了分析。还分析了存储和交织程度之间以及总线宽度和总线速度之间在功耗、性能和成本方面的权衡。教育计划包括开发一门关于存储系统设计和优化的课程。

The gap between the processor and memory speeds is a major bottleneck in today's computer systems. Increasing DRAM bandwidth and reducing access time are keys to solving the memory latency problem. There is a relative dearth of architecture studies on DRAM devices and systems; there are therefore many fundamental questions representing open research in the field. This project investigates into the effects of various techniques in designing a DRAM system. Examples include supporting concurrent accesses and determining the extent to which modern CPUs can exploit such support; the effect of multiple channels and whether they be ganged together to increase bandwidth or should they operate independently; and the effect of banking and its optimal degree for DSP and embedded applications. For burst-mode DRAMs, the optimal burst size to accommodate both concurrency and fast end-to-end latency is analyzed in this project. The tradeoffs between the degrees of banking and interleaving, and between bus width and bus speed in power, performance, and cost are also analyzed. The educational plan involves developing a course on memory-systems design and optimization.