CAREER:The Evaluation and Design of a Scalable, High Performance and Energy Efficient Microprocessor Architecture

推测执行已被广泛应用于计算机体系结构研究中，以追求更高层次的指令级并行性。然而，最近的研究表明，这种技术可以显著影响处理器管道的可扩展性。这项研究将调查一些关于性能、可扩展性、能源效率、面积成本和复杂性的推测性技术；最终形成一种新颖的、可扩展的架构，在未来的技术规模上提供高性能。这种架构将最小化处理器关键时序路径上的逻辑量，依靠小型推测结构来减少处理器的周期时间。在关键路径之外，各种较大的投机结构为关键路径提供支持。本文研究的技术包括分支预测、值和地址预测、数据预取、早期寄存器释放和后期寄存器分配以及多聚类功能单元。这些技术中的许多都需要大型且通常复杂的预测器，这些预测器可能会影响处理器的周期时间和功率密度。本研究探讨了一些技术，以减少这些结构的访问时间和尺寸，同时仍然提供准确性，以避免昂贵的投机回收程序。

Speculative execution has been widely used in computer architectureresearch in the pursuit of higher levels of instruction levelparallelism. However, recent studies have shown that this techniquecan significantly impact the scalability of the processor pipeline.This research will investigate a number of speculative techniqueswith respect to performance, scalability, energy efficiency, areacosts, and complexity; eventually leading to a novel, scalablearchitecture to provide high performance at future technology sizes.Such an architecture will minimize the amount of logic on thecritical timing path of the processor, relying on small speculativestructures to reduce the cycle time of the processor. Off thecritical path, a variety of larger speculative structures provide abacking store to the critical path.Some of the techniques to be examined in this research includebranch prediction, value and address prediction, data prefetching,early register release and late register allocation, and multipleclustered functional units. Many of these techniques require largeand often complex predictors that can impact the cycle time and powerdensity of a processor. This research investigates some techniquesto reduce the access time and size of these structures, while stillproviding the accuracy to avoid costly speculative recoveryprocedures.